{
    "meta": {
        "title": "D-Central — ASIC Control Board Reference",
        "description": "Reference for 12 Bitcoin ASIC miner control boards (the controller that drives the hashboards): SoC, CPU, models, hashboard chip family, PIC vs No-PIC, host interface and flash notes.",
        "generated": "2026-06-21T02:09:27+00:00",
        "version": "1.0",
        "license": "https://creativecommons.org/licenses/by/4.0/",
        "license_name": "CC BY 4.0",
        "source": "https://d-central.tech/asic-control-board-reference/",
        "record_count": 12,
        "provenance": "D-Central Mining Bible (ANTMINER_ARCHITECTURE + MASTER_CHIP_CATALOG) + the Laval ASIC repair bench.",
        "disclaimer": "A reference: control-board revisions vary within a model line. Confirm the exact board markings (SoC, NAND, connector) before flashing or swapping a controller."
    },
    "rows": [
        {
            "id": "zynq-s9-gen",
            "board": "Xilinx Zynq controller (S9-gen; zynq7007 BMU prefix; am1-s9)",
            "soc": "Xilinx Zynq-7010 (XC7Z010; XC7Z007S variant) with Artix-7 FPGA fabric",
            "cpu": "Dual ARM Cortex-A9 @ 667 MHz (Zynq-7010)",
            "models": "S9 / S9i / S9j / T9+ / S9D / R4",
            "chip_family": "BM1387 (SHA-256)",
            "pic": "PIC (PIC16F1704, x3 at I2C 0x55/0x56/0x57)",
            "interface": "FPGA UART FIFOs (AXI 0x43C00000) + FPGA AXI-IIC (0x41600000) -> ASIC chain",
            "notes": "Boots FSBL + FPGA bitstream + U-Boot from 256MB NAND (or SD via J3 jumper); the root ramdisk is only SHA256-verified, so a DCENT_OS image can replace it while reusing the stock boot chain, building on community open tooling.",
            "bible_source": "ANTMINER_ARCHITECTURE.md (Control Board Specs L32-90; I2C Bus Map L304-318); MASTER_CHIP_CATALOG.md (10.5 + 7 PIC table)"
        },
        {
            "id": "zynq-s17-gen",
            "board": "Xilinx Zynq controller (S17/T17-gen; am2-s17)",
            "soc": "Xilinx Zynq-7000 class (XC7Z010 / XC7Z007S) with FPGA fabric",
            "cpu": "Dual ARM Cortex-A9 @ 667 MHz (Zynq-7010 class)",
            "models": "S17 / S17+ / T17 / T17+",
            "chip_family": "BM1397 (SHA-256)",
            "pic": "PIC (dsPIC33EP16GS202)",
            "interface": "FPGA UART FIFOs (AXI) -> ASIC chain",
            "notes": "Same Zynq boot chain as the S9 generation but with a 4.6.x kernel; aftermarket OS images typically replace only the NAND ramdisk and reuse the stock FSBL/FPGA, which eases a DCENT_OS port.",
            "bible_source": "MASTER_CHIP_CATALOG.md (10.5: Zynq am2-s17 = BM1397, dsPIC33EP16GS202)"
        },
        {
            "id": "zynq-s19-gen",
            "board": "Xilinx Zynq controller (S19/T19-gen; C55/C71; am2)",
            "soc": "Xilinx Zynq-7010 (XC7Z007S/010) with Artix-7 FPGA fabric",
            "cpu": "Dual ARM Cortex-A9 @ 667 MHz (Zynq-7010)",
            "models": "S19 / S19 Pro / S19a / S19a Pro (early Zynq C55/C71 boards)",
            "chip_family": "BM1398 (SHA-256)",
            "pic": "PIC (dsPIC33EP16GS202)",
            "interface": "FPGA UART FIFOs (AXI) + FPGA I2C -> ASIC chain",
            "notes": "C55/C71 boards boot Zynq FSBL + FPGA + U-Boot from NAND with an external SD-recovery slot; DCENT_OS targets them via the same SHA256-only ramdisk-replacement path used on the S9-gen board.",
            "bible_source": "ANTMINER_ARCHITECTURE.md (S19 system diagram L4-30); CONTROL_BOARD_SECURITY.md (8.2 C55/C71 = XC7Z007S/010); MASTER_CHIP_CATALOG.md (10.5: Zynq am2 = BM1398)"
        },
        {
            "id": "zynq-l7",
            "board": "Xilinx Zynq controller (L7 Scrypt; xil-L7)",
            "soc": "Xilinx Zynq-7000 class (XC7Z010 family; exact part uncertain) with FPGA fabric",
            "cpu": "Dual ARM Cortex-A9 (Zynq-7000 class; clock not separately stated)",
            "models": "L7 / L7 Hydro (Scrypt)",
            "chip_family": "BM1489 (Scrypt)",
            "pic": "uncertain (PSU enable on GPIO907; voltage-controller type not identified)",
            "interface": "FPGA UART FIFOs (AXI) -> ASIC chain",
            "notes": "Scrypt-class Zynq controller whose init only sets PSU-enable (gpio907) and LEDs, with the hashboard chain brought up over FPGA UART; a DCENT_OS Scrypt path would mirror the SHA-256 UART driver model.",
            "bible_source": "MASTER_CHIP_CATALOG.md (10.5: Zynq xil L7 = BM1489); wave6-mining/B1 inits.md (5: L7 gpio907 psu_en)"
        },
        {
            "id": "beaglebone-am335x",
            "board": "BeagleBone-style AM335x controller (BBCtrl / BB18)",
            "soc": "TI AM335x Sitara (AM3352 in the board table)",
            "cpu": "Single ARM Cortex-A8 (clock not stated in Bible)",
            "models": "L3+ / L3++ (Scrypt); late-2021 S19j / S19j Pro stock-BB (BB18 board)",
            "chip_family": "BM1485 (L3+, Scrypt); BM1398 / BM1362 (S19j-era stock-BB)",
            "pic": "PIC present (L3+ PIC mac-pairing; dsPIC33EP on S19j-era stock-BB)",
            "interface": "Software UART (/dev/ttyO1,2,4) + Linux I2C; no FPGA",
            "notes": "No FPGA and no kernel modules - ASIC chains are driven over standard Linux UARTs, making this the simplest DCENT_OS target; boots MLO -> U-Boot -> kernel -> ramdisk from NAND or an internal SD card.",
            "bible_source": "ANTMINER_ARCHITECTURE.md (BeagleBone L92-105); wave6-mining/B1 inits.md (3 L3+ BBB GPIO map)"
        },
        {
            "id": "cvitek-cv1835",
            "board": "Cvitek CV1835 controller (CVCtrl / C88, CB8, CB4)",
            "soc": "Cvitek/SOPHGO CV1835 (CV183x family)",
            "cpu": "Dual ARM Cortex-A53 @ 1.0 GHz (ARMv8-A; runs AArch32 under stock firmware)",
            "models": "S19k Pro / S19 XP / S19j Pro / S19j XP / S21 / T21 / KS3 / KS5 / X5 / L9 (C88/CB8/CB4 boards)",
            "chip_family": "BM1362 / BM1366 / BM1368 (S21) / BM1489 (L9)",
            "pic": "PIC (dsPIC33EP)",
            "interface": "UART (stock uart_trans.ko or userspace software UART) + Linux I2C; no FPGA",
            "notes": "Boots an ATF FIP chain (FSBL + OpenSBI + U-Boot) from SPI-NAND with secure boot; third-party OS images commonly run as a reboot-non-persistent overlay, so a clean DCENT_OS install needs network re-injection or a board with the external SD slot.",
            "bible_source": "CONTROL_BOARD_SECURITY.md (1-3 CV1835 arch; 8.2 board table); MASTER_CHIP_CATALOG.md (10.5: Cvitek CV1835 = BM1362/BM1366)"
        },
        {
            "id": "amlogic-axg",
            "board": "Amlogic AXG controller (AMLCtrl / am3-aml; C76, C81, C83, CBE)",
            "soc": "Amlogic A113D (AXG SoC family)",
            "cpu": "Quad-core ARM Cortex-A53 @ 1.2 GHz (ARMv8-A; ARM64 kernel, armhf userspace)",
            "models": "S19j Pro / S19 XP / S19k Pro / S21 / S21 Pro / S21 XP / S21+ / L9 (C76/C81/C83/CBE boards)",
            "chip_family": "BM1362 / BM1366 / BM1368 / BM1370 / BM1489 (L9)",
            "pic": "PIC (dsPIC33EP) on S19j-era boards; No-PIC on S21 generation (TAS5782M DAC drives VID)",
            "interface": "Software UART (/dev/ttyS1-4) + Linux I2C; no FPGA",
            "notes": "Quad-A53 AXG with secure boot from SPI-NAND and micro-USB OTG recovery (firmware-blocked on units shipped Sept 2025+); S21-gen boards drop the PIC, consistent with the chip canon, and share a common power-on init across the S21 family.",
            "bible_source": "ANTMINER_ARCHITECTURE.md (Amlogic L107-136); CONTROL_BOARD_SECURITY.md (4 A113D; 8.2 C76/C81/C83/CBE); MASTER_CHIP_CATALOG.md (7 NoPic/TAS5782M; 10.5 AML)"
        },
        {
            "id": "esp32-s3-bitaxe",
            "board": "ESP32-S3 self-contained controller (BitAxe-class open hardware)",
            "soc": "Espressif ESP32-S3",
            "cpu": "Espressif ESP32-S3 microcontroller",
            "models": "BitAxe Ultra / Hex Supra (BM1366), BitSupra (BM1368), BitAxe Gamma (BM1370), BitAxe Touch (BM1370, planned) and similar open single-board miners",
            "chip_family": "BM1366 / BM1368 / BM1370 (single-chip)",
            "pic": "No-PIC (TPS546 buck regulator; single ASIC)",
            "interface": "UART + I2C direct to a single ASIC",
            "notes": "Self-contained open-hardware controller driving one ASIC over UART+I2C with a TPS546 buck regulator; firmware is flashed directly over USB, making it the most accessible DCENT-class target and the spirit of building on prior open work.",
            "bible_source": "MASTER_CHIP_CATALOG.md (6 ESP32-S3 BitAxe; 10.5 TPS546). Gamma=BM1370 per 15+ Bible docs (catalog L96/225 is the isolated error)"
        },
        {
            "id": "allwinner-whatsminer",
            "board": "Allwinner H-series controller (WhatsMiner / MicroBT; H3, H6, H616)",
            "soc": "Allwinner H3 / H6 / H616",
            "cpu": "Allwinner H3 / H6 / H616 (cores not detailed in Bible)",
            "models": "WhatsMiner M1-M3 / M8-M12 / M19-M20S / M50-M60S / D-series (MicroBT)",
            "chip_family": "MicroBT K-series (K1/K2/K3/D) - not Bitmain BM",
            "pic": "No-PIC (UART command-byte voltage control)",
            "interface": "UART command-byte protocol (per-model profile from EEPROM chip_id via UCI)",
            "notes": "OpenWrt/procd controller where cgminer selects a per-model UCI profile from the EEPROM chip_id and drives the chain over a UART command-byte protocol.",
            "bible_source": "MASTER_CHIP_CATALOG.md (3 K-series chip_id; 10.5: Allwinner H3/H6/H616); wave6-mining/B3 inits.md (11-12)"
        },
        {
            "id": "innosilicon-armv7",
            "board": "Innosilicon ARMv7 controller (T-series)",
            "soc": "Custom Innosilicon ARMv7 SoC",
            "cpu": "Custom Innosilicon ARMv7 SoC (cores not detailed in Bible)",
            "models": "Innosilicon T2Tz (DragonMint-T1 heritage T-series)",
            "chip_family": "Innosilicon T2T - not Bitmain BM",
            "pic": "uncertain (mcompat HAL PWM voltage backend; not PIC-based)",
            "interface": "uncertain (mcompat HAL, PWM_SOC_HUB backend)",
            "notes": "Custom ARMv7 SoC running a cgminer fork with an mcompat hardware-abstraction layer for voltage/PWM.",
            "bible_source": "MASTER_CHIP_CATALOG.md (5 Innosilicon T-series, GAP C; 10.5); wave6-mining/B3 inits.md (8-10)"
        },
        {
            "id": "k210-avalon",
            "board": "Kendryte K210 controller (Avalon industrial; bare-metal)",
            "soc": "Kendryte K210 (RISC-V)",
            "cpu": "Kendryte K210 (RISC-V; bare-metal, no Linux init)",
            "models": "Avalon A1346 / A14x / A15x (Canaan industrial)",
            "chip_family": "Canaan Avalon A3197S / A3198S / A3200C-Plus - not Bitmain BM",
            "pic": "uncertain (voltage control encrypted in mm_miner firmware)",
            "interface": "uncertain (encrypted mm_miner; K210 SPI-flash bootloader -> main loop)",
            "notes": "Bare-metal RISC-V controller with no Linux init; the mm_miner image is AES-CBC encrypted with the key in K210 OTP eFuse, so the platform is effectively closed to custom firmware.",
            "bible_source": "MASTER_CHIP_CATALOG.md (4 Avalon chips, GAP A; 10.5: K210 RISC-V); wave6-mining/B3 inits.md (14)"
        },
        {
            "id": "k230-avalon",
            "board": "Kendryte K230 Linux controller (Avalon home-class)",
            "soc": "Kendryte K230 (RISC-V)",
            "cpu": "Kendryte K230 (RISC-V; runs Linux)",
            "models": "Avalon Nano 3 / 3S / Mini 3 (Canaan home-class; some fields uncertain)",
            "chip_family": "Canaan Avalon home-class chips (uncertain) - not Bitmain BM",
            "pic": "uncertain",
            "interface": "uncertain",
            "notes": "Newer RISC-V controller that runs Linux on Canaan's home-class miners (incl. the Avalon Mini 3); board and chip details still flagged TBD in the Bible.",
            "bible_source": "MASTER_CHIP_CATALOG.md (10.5: K230 RISC-V Linux (Avalon home))"
        }
    ]
}