Bitaxe Hex – Asymmetric Per-Domain Hashrate (BM1368 Unbalanced)

Confirm asymmetry on a clean baseline before touching anything. Open AxeOS dashboard -> System Info / per-chip stats grid. Set the Hex to STOCK tune (no overclock, no undervolt) via Settings, full power-cycle (unplug XT30 main power AND USB-C, wait 60 seconds, reconnect both). Let it run 30 minutes to thermal steady-state. Screenshot the per-chip GH/s and per-chip temperature columns. The reference question: is the worst chip more than 30% below the median of the other five? If yes, you are in the right triage. If the deficit is under 15%, this is normal silicon-lottery variance, not a fault.

Read the serial console boot log to confirm the chain enumerates cleanly. USB-C data cable PC-to-Hex, terminal at 115200 baud 8N1, power-cycle from the main PSU. Watch for Chip 0 response through Chip 5 response and a final Chip count: 6. If the chain enumerates fully, the fault is not a chain break - it is a single chip that handshakes but mis-hashes (this page). If the log shows Chip N no response, you are on the wrong page - jump to the Bitaxe Hex - One Chip Dead (5 of 6 Hashing) playbook instead. Save the screenshot regardless - any future support ticket will need it.

Re-flash the correct ESP-Miner-multichip image via Bitaxe Web Flasher. Open bitaxeorg.github.io/bitaxe-web-flasher/ in Chrome or Edge (Web Serial required). Pick the EXACT multichip image for Hex AND your board revision (Supra Hex / Hex 702 / older Hex differ). Flash, full power-cycle, retest baseline. NVS factory-reset via Settings -> Restore Defaults if the asymmetry persists. A non-trivial fraction of per-chip-imbalance reports trace back to a stale NVS preset that pinned one chip to a different frequency than its siblings.

DMM the 12 V rail under load before blaming the chip. Open-circuit at the XT30 must read 12.0-12.6 V. Apply a 6-8 A load (halogen bulb, electronic load) and re-measure - must hold at or above 11.5 V sustained. Voltage sag under transient draw can starve the per-chip DCDC regulators asymmetrically because the chip physically farthest from the input bulk caps loses regulation first. A bad PSU often presents as 'one chip is weaker' rather than as a clean rail-down event. If the rail sags, swap to a known-good 12 V / 5-8 A regulated brick before doing chip-level work.

Probe per-chip Vcore at the test points while AxeOS is hashing at idle workload. DMM on DC volts, GND on the chassis ground point, probe each chip's Vcore test point (silkscreened on most revisions; reference bitaxeorg hardware schematics for your revision). All six should read 1.20-1.30 V within 30 mV of each other. If the underperforming chip reads notably lower (1.10-1.18 V), the per-chip DCDC converter feeding that chip is the suspect, not the chip itself. Note which test point belongs to which physical chip - critical for Tier 3.

Scope the per-chip DCDC output ripple. With a 100 MHz handheld scope on AC-coupled mode, probe each chip's Vcore test point under hashing load. Healthy: ripple under 30 mV peak-to-peak. Faulty per-chip DCDC: ripple jumps to 100 mV+ peak-to-peak, often with low-frequency oscillation. Excessive ripple destabilizes the BM1368 internal hash engines and shows up exactly as the per-chip HW% spike + per-chip GH/s deficit pattern. If ripple is excessive on the named chip's domain only, the converter or its filtering is damaged and Tier 3 / Tier 4 chip-domain repair is needed.

IR thermometer or thermal camera the heatsink top-side under hashing load. Let the Hex run at full workload for 15 minutes. Sweep an IR gun across the heatsink directly above each chip position - or better, take a thermal photo with a FLIR ONE Pro. Healthy Hex: chip-to-chip delta-T at the heatsink is under 5 C across all six chips. Asymmetric pattern: the underperforming chip shows a COLD spot 8-15 C below siblings (less work = less heat) - confirms the deficit is silicon / handshake / ripple level, not a thermal-management failure. A HOT spot would mean the chip is doing the work but venting it badly (paste / mount issue) - different fix path, see Tier 2 remount.

Power off, unplug everything, remove the heatsink. Inspect the thermal interface above EACH chip. Healthy: paste / pad evenly squeezed, no air gaps, no pump-out trails. Paste pump-out: the named chip shows a dry center spot with paste pushed out to the edges - over months of thermal cycling the paste viscosity changes and migrates off the die center, raising junction temperature on that chip alone. Fix: clean off the old paste with isopropyl 99%, apply a thin even layer of Arctic MX-6 or Thermal Grizzly Kryonaut, remount with finger-tight-plus-quarter-turn on each screw (NOT cranked - over-torque flexes the long Hex PCB).

Inspect the heatsink mount geometry for asymmetry. With the heatsink off, lay the bare Hex flat on a table - any visible PCB bow under the named chip's position? Inspect the heatsink contact face under good light - any visible nick, scratch, or contamination above the named chip's footprint? D-Central Hex heatsinks (we manufactured the first ones) are CNC-flat across all six chip positions; an aftermarket or modified heatsink with uneven contact pressure will under-pressure one chip. Fix: replace with a known-flat heatsink (D-Central original Hex heatsink is the reference part), thin paste, finger-tight-plus-quarter-turn remount.

Verify all per-chip frequency / voltage settings in AxeOS are uniform. AxeOS exposes per-chip frequency on multichip firmware; some preset profiles or stale NVS state can pin one chip to a different value than its siblings. Check Settings -> per-chip overrides (where present) and confirm all six chips share the same frequency and the same voltage offset. Reset to global stock if uncertain. Watch the per-chip GH/s grid for 30 minutes after the reset - if symmetry returns, the asymmetry was firmware / config and not hardware.

Cross-reference the AxeOS per-chip number with the physical chip layout on the board. The AxeOS chip index (Chip 0-5) maps to specific physical positions on the silkscreen (U1-U6 or similar per revision - reference bitaxeorg schematics for your Hex revision). Identify the exact physical chip BEFORE Tier 3, because every subsequent step is about that one chip. If the physical chip is at a chain-end position (silicon-lottery hot-spot for thermal-cycling damage), Tier 3 reflow becomes higher-confidence; if it is mid-chain, suspect domain-trace or local capacitor damage first.

Tier 3 - single-chip reflow on the named BM1368. Mask adjacent chips with aluminium foil cut to fit (leave a small airflow gap) or Kapton tape. Place the Hex on a preheater at 150 C bottom-side - a real preheater, NOT a hot plate (uneven heating across a long Hex board lifts pads). Apply hot air top-side at 310-330 C, moving in small circles over the named chip for 30 seconds. Do NOT stop on one spot for more than 3-4 seconds or adjacent 0402 caps will lift and tombstone. Cool naturally on the preheater to 80 C, then to ambient. Re-paste, remount, re-flash multichip firmware, retest per-chip symmetry.

Tier 3 - single-BM1368 replacement if reflow fails. If post-reflow the chip still under-performs by 30%+, the silicon itself is degraded (gate-oxide damage from a prior overvoltage event, ESD damage to an internal hash engine, or simply early-life chip failure). Desolder with hot air + low-melt solder / Chip Quik, lift cleanly, clean pads with braid + flux, place a replacement BM1368 (D-Central graded inventory or reliable supplier with verified date code), reflow with proper BGA thermal profile, microscope-inspect alignment before powering. Re-paste, remount, re-flash multichip firmware, verify per-chip symmetry returned within 5%.

Tier 3 - inspect the per-chip DCDC domain components if Vcore was off in Step 5. Each BM1368 has its own local regulator network with bulk + decoupling capacitance and a feedback resistor divider. With the heatsink off, microscope-inspect the components feeding the named chip's Vcore. Look for: blown SMD inductor (open-circuit measurement on a DMM), bulging or split bulk cap, cracked MLCC near the chip, lifted pad on the feedback resistor. Replace any visibly damaged passive with the same value (reference bitaxeorg hardware schematics for the BOM). After repair, re-verify Vcore at Step 5 before declaring complete.

Tier 3 - re-flash multichip firmware after ANY chip-level rework. Hot-air work briefly raises SPI flash temperature and can corrupt data silently. After any chip-level rework, re-flash the correct ESP-Miner-multichip image via Web Flasher BEFORE full-load validation. NVS factory-reset, full power-cycle, then verify per-chip GH/s symmetry across 30 minutes of steady hashing. Common pitfall: hardware fix is good but leftover rework-induced flash corruption masks the recovery - always re-flash, always re-verify.

Tier 4 - stop DIY on BGA rework if you do not have a real preheater + controlled-temperature hot-air station + rework microscope. BM1368 is a BGA package - iron-only rework is not a path. Without a preheater, the thermal gradient across a long Hex board rips pads off. Without controlled temperature, you will char the FR-4 or blow adjacent passives. Without a microscope, alignment is guesswork and solder bridges are guaranteed. Ship the Hex to D-Central. Bench has Hakko preheaters, Quick / Hakko hot-air stations, stereo microscopes, reflow ovens, and BM1368 inventory on the shelf.

Tier 4 - stop DIY if the asymmetry is intermittent or shifts between chips on different cold-boots. Inconsistent per-chip outlier patterns (chip 4 weak today, chip 2 weak tomorrow) point at scope-level signal-integrity issues on the daisy chain or a marginal shared component upstream of multiple domains. Diagnosing intermittent multi-chip Hex problems takes hours of controlled bench time, thermal bake-out testing, and scope work that is not practical at home. D-Central has the rigs and the time-cost economics work in your favour - ship it.

Tier 4 - ship to D-Central with full diagnostic context. Pack the Hex in an anti-static bag, include the original PSU (we test against your exact power stack), attach a note with: AxeOS per-chip GH/s screenshot showing the asymmetry, serial console boot log, board revision (silkscreen), firmware version, Tier 1/2 steps already tried, observed pattern (consistent vs intermittent, cold vs warm, recent re-paste / move / surge), and any context. Canada-wide shipping, US/international welcomed. Turnaround 5-10 business days. D-Central pioneered the Bitaxe Hex heatsink and keeps BM1368 inventory in-house for single-chip swaps.

Tier 4 - repair economics on Hex asymmetry. A Tier-4 single-BM1368 swap at D-Central runs CAD $95-185 depending on chip sourcing and labour time. Two-chip swap: CAD $175-330. Per-chip DCDC component-level repair: CAD $60-150. A new Bitaxe Hex board runs CAD $220-320 depending on variant (Supra Hex / Hex 702). One-chip and two-chip repairs almost always favour fixing over replacing - one more Hex on the network is one more vote against pool centralization. Three-plus chip damage starts to lean toward replacement; we will say so up front. Open hardware means an honest conversation.

Log the repair history for fleet-level pattern detection. Whatever the outcome, record in your mining log: date the asymmetry started, which chip position drifted low, AxeOS per-chip GH/s fingerprint, ambient temperature, runtime hours on the board, last heatsink re-paste date, recent move / surge / firmware-flash events. If you run multiple Hex units (solo-mining stack, basement heat-recovery rig), the pattern across the fleet tells you whether failures are random silicon lottery or systemic (PSU brand, ambient profile, paste age, firmware regression). Hex is a six-chip thermal-cycling endurance test - treat it like one.