Controlled Impedance

Controlled impedance is the practice of designing a PCB trace so its characteristic impedance stays within a specified tolerance of a target value, most commonly 50 ohms single-ended or 90 to 100 ohms differential. At the data rates inside a modern ASIC miner's control board, copper traces stop behaving like ideal wires and start behaving like transmission lines: if the impedance a signal sees changes abruptly along its path, part of the signal energy reflects back toward the source, corrupting the waveform with ringing and overshoot. Holding impedance constant from driver to receiver keeps reflections small and edges clean, which is the difference between a link that works for years and one that throws intermittent errors nobody can reproduce.

What sets the impedance

Characteristic impedance is fixed by physical geometry, not by any component. It depends on the trace width and copper thickness, the height of dielectric separating the trace from its reference plane, and the dielectric constant (Dk) of the laminate. A wider trace or thinner dielectric lowers impedance; a narrower trace or thicker dielectric raises it. A fabricator hits the target by adjusting trace width for a given PCB stackup, then verifies the result with a test coupon measured by TDR (time-domain reflectometry). Designers request impedance control explicitly on the fabrication drawing, because the board house must tune its etching compensation and layer spacing to comply — an ordinary "build to Gerbers" order gets no such guarantee. Every via, connector, and reference-plane gap along the route is a potential discontinuity, which is why high-speed routing discipline is as much about what sits under the trace as the trace itself.

Why it matters in mining hardware

Hashboards and control boards carry high-speed clock and data lines between the SoC, PLLs, and the ASIC chain — the daisy-chained UART-style signalling that lets a Zynq SoC or its successors enumerate dozens of chips per board. Uncontrolled impedance shows up as edge ringing, marginal timing, and the classic hard-to-diagnose field symptoms: boards that hash at low frequency but fall over when pushed, chips that enumerate on cold boot but drop out warm, error counts that climb with ambient temperature. The signal chain crosses domain-boundary resistors where a single cold joint already threatens continuity; adding impedance discontinuities on top narrows the margin further.

Implications for the repair bench

Repair work can quietly destroy impedance that the factory paid to control. Reworking a connector with excess solder, running a jumper wire across a damaged trace, or lifting a section of trace off its reference plane all create local discontinuities. The practical rules: keep any bodge wire on a signal-critical net as short as physically possible, route it directly over the ground plane rather than flying through the air, and never widen or neck a high-speed trace during a patch repair. If a repaired board passes at stock frequency but fails under overclock, suspect signal integrity before blaming the chip. For structural repairs that expose inner layers, remember that the reference plane is part of the transmission line — a gouge into the plane under a clock trace is a signal defect, not just cosmetic damage. If a board's faults resist bench diagnosis, a professional evaluation through D-Central's repair service is cheaper than chasing ghosts.

For related signal-integrity concepts see differential pair, via, and copper pour.

Impedance control also costs real money at the fab, which is why hashboard designers specify it only on the nets that need it and let power routing and slow control signals run on ordinary geometry. Reading a board this way is a useful bench skill: the consistently spaced, deliberately uniform traces snaking between the chips are the ones carrying timing-critical signals, and they are the ones a careless repair should never widen, reroute, or lift.