GAAFET (Gate-All-Around)

GAAFET (gate-all-around field-effect transistor) is the successor to the FinFET as the workhorse transistor of leading-edge chip manufacturing. Where a FinFET's gate wraps a vertical silicon fin on three sides, a GAAFET's gate completely encircles the channel on all four — in the mainstream implementation, the fin is replaced by a vertical stack of thin, ribbon-like silicon channels called nanosheets, each fully wrapped in gate material. That maximal wrap gives the strongest electrostatic control over the channel yet achieved in volume production: less leakage when the transistor is off, sharper switching when it turns on, and usable performance at lower supply voltages. For Bitcoin mining silicon, whose entire competition is joules per terahash, that control is the next efficiency dividend.

Why the fin ran out of road

Transistor scaling is a battle against leakage: as channels shrink, the gate loses authority and current sneaks through even when the device should be off. The FinFET's three-sided wrap solved that problem for a decade, but below roughly the 3 nm class the fin itself becomes the limit — it cannot be made thin enough, at manufacturable yield, for three-sided control to suffice, and its quantized width (you can only add or remove whole fins) makes fine-grained tuning coarse. Wrapping the gate all the way around is the endgame of the geometry: there is no fourth side left to lose control from.

Nanosheets and the efficiency dividend

Stacked nanosheets bring a second, subtler advantage: the sheet width is a nearly continuous design variable. Designers can widen sheets for high-drive speed-critical paths or narrow them for low-power logic — without changing the footprint — where FinFET design could only step between whole fins. For an ASIC that is essentially an ocean of identical SHA-256 logic, that tunability maps directly onto the efficiency race: the same die area can be biased toward lower joules per terahash. TSMC quotes its first GAA node, N2 (2 nm), at roughly 10–15% more speed at the same power, or 25–30% less power at the same speed, versus its final FinFET generation — and in mining, the buyer captures that almost entirely as efficiency, since power is the dominant lifetime cost. Each such node step is what separates one ASIC generation's ~15 J/TH from the next one's target.

Who shipped it, and when it reaches miners

Samsung reached high-volume GAA first, putting its 3 nm nanosheet process into mass production in June 2022. TSMC held FinFET through 3 nm and adopted nanosheet GAA at N2, entering volume production in late 2025. Intel's variant, RibbonFET, is the same architectural idea under its own branding. All three converged on gate-all-around for the same reason: past the 3 nm class, the fin simply runs out of control margin. Mining chips historically adopt new nodes a beat behind smartphone silicon — leading-edge wafer capacity goes to the highest bidders first — but the trajectory is fixed: the ASIC generations that follow today's 5 nm and 3 nm parts will be GAA parts, and their efficiency gains will retire another tranche of older hardware to the resale market and the repair bench.

Placing it in the stack

The GAAFET is a device architecture, not a process node by itself: it is patterned with EUV lithography, and each node built from it is ultimately judged by transistor density and by power-performance numbers, not by its marketing name. Beyond nanosheets, the roadmap points to CFETs — stacking n-type and p-type devices vertically atop one another — but that is the next fight. For now, gate-all-around is where the transistor stands, and every future J/TH headline in mining will be built on it.