Multi-Patterning

Multi-patterning is a family of semiconductor fabrication techniques that print a single chip layer using more than one exposure or deposition step, so that the final feature pitch is tighter than any single lithography exposure could resolve. It is how the industry kept shrinking transistors below the 20nm node for years while still using 193nm deep-ultraviolet light — printing features dozens of times smaller than the wavelength doing the printing — and it remains essential today even alongside EUV for the very densest layers of advanced chips, including the mining ASICs built on 7nm and 5nm class processes.

Pitch-splitting: LELE and friends

The most direct form is litho-etch-litho-etch (LELE) double patterning: a dense target pattern is decomposed into two sparser patterns, each comfortably within the resolution of one exposure, printed and etched in sequence so their features interleave and double the final line density. The catch is overlay: the second exposure must align to the first within nanometers, and any misregistration becomes a spacing error in the finished layer. Decomposing a layout into printable halves is itself a hard computational problem — some geometries cannot be split at all, so multi-patterning reaches backward into design rules, constraining what chip designers may draw in the first place.

Self-aligned spacers: SADP and SAQP

A more elegant variant sidesteps overlay error. Self-aligned double patterning (SADP) prints "mandrel" lines at a relaxed pitch, conformally deposits a thin film over them, then anisotropically etches it so only the sidewall spacers remain — two per mandrel. Removing the mandrels leaves twice as many lines, positioned by film thickness rather than by a second alignment, which is why the technique is called self-aligned. Repeating the trick on the spacers themselves yields self-aligned quadruple patterning (SAQP), quadrupling density from one exposure. SADP and SAQP became the workhorses for the tightest regular patterns — transistor fins and lower metal lines — precisely because deposition thickness is controllable to fractions of a nanometer.

The economics, and the EUV trade-off

Every additional pass costs a mask, multiple process steps, another trip through the fab's most expensive tools, and another opportunity for defects and misalignment to kill die — pressure that shows up directly in semiconductor yield and in the size of the mask set a design must pay for. That economic burden is the main reason the industry spent two decades and tens of billions of dollars developing 13.5nm EUV lithography: one EUV exposure can replace three or four DUV multi-patterning passes on a critical layer, simplifying the flow even though the EUV tool itself costs vastly more per hour. The trade never fully resolves — at the leading edge, the densest layers now require EUV plus multi-patterning, restarting the cycle at a finer scale.

Why it matters to mining hardware

Multi-patterning also reshaped chip design itself. Layers printed in multiple passes must be "colored" — every feature assigned to one exposure — and layouts that cannot be legally colored are simply forbidden, so routing tools, standard-cell libraries, and design-rule decks all carry the fingerprints of the patterning scheme underneath them. A physical-fab constraint thus propagates all the way up into what circuits a designer is allowed to draw.

The efficiency race in Bitcoin ASICs is ultimately a fabrication race: each process generation packs more SHA-256 logic into fewer joules, and multi-patterning is part of how 7nm-class chips like the BM1397 and the 5nm-class generations after it became printable at all. It is also part of why leading-edge wafers are expensive and why only a handful of foundries can produce competitive mining silicon — every extra patterning pass raises the barrier. Multi-patterning works hand in hand with photolithography fundamentals and EUV to deliver the transistor density behind every modern hashboard.