Tape-Out

Tape-out is the point in chip development at which the design is considered final and the complete layout database is released to the foundry for manufacturing. The name is a holdover from the era when the design data was written onto magnetic tape and physically delivered. Today it is a digital handoff of mask-layout files, but it remains the irreversible commitment that turns a design into silicon — the moment a chip company stops iterating and starts spending serious money.

What happens at tape-out

Before tape-out, the layout must pass exhaustive verification. Design-rule checking (DRC) confirms every geometric feature respects the foundry's manufacturing limits — minimum widths, spacings, densities — while layout-versus-schematic (LVS) comparison confirms the physical layout is electrically identical to the intended circuit. Timing signoff, power analysis, and parasitic extraction round out the checklist. Once approved, the foundry uses the tape-out files to produce the photomask set that will pattern each layer of the chip onto wafers. Errors discovered after this stage are brutally expensive: correcting them means a "re-spin" — new masks, new wafer runs, and months of lost schedule. At advanced process nodes, a full mask set alone costs millions of dollars, which is why verification consumes such a large share of any chip project.

Why it matters for mining hardware

Every new generation of mining ASIC represents a tape-out backed by an enormous, non-refundable bet on mask and wafer costs. This is why ASIC vendors release chips in discrete generations rather than continuously — the BM1398 powering the S19 family, the BM1368 in the S21, the BM1370 in the S21 Pro and XP each represent a separate tape-out that only pays off across a high-volume production run. It also shapes the industry's structure: the capital wall of a leading-edge tape-out is a major reason so few companies design competitive SHA-256 ASICs, and why efficiency gains arrive in step changes tied to new silicon rather than smooth curves. A design flaw that survives to tape-out cannot be firmware-patched away if it lives in the datapath — the vendor either eats a re-spin or ships around the bug, and miners live with the consequences for the life of the hardware.

Tape-out and the open-hardware question

Tape-out is also where the economics of open ASICs get honest. Publishing RTL source code is cheap; taping out is not. Community and open-source mining chip efforts must either target older, cheaper process nodes, share multi-project wafer runs, or find backers willing to fund masks — which is why open innovation in mining has historically flourished one level up, in firmware, control boards, and complete devices like the Bitaxe that build on commercially fabricated chips. Understanding tape-out costs explains that landscape better than any ideology does: the chips are proprietary because the masks are expensive, and the openness lives where the marginal cost of sharing is near zero.

From tape-out to your shelf

Tape-out starts a long pipeline. Wafers take weeks to months to move through the foundry's process steps; finished wafers are then tested, diced, and packaged; and the packaged chips are binned by measured performance, since even adjacent dies from one wafer differ in speed and leakage. Binning is why a single tape-out fans out into multiple product tiers — the same silicon design ships at different hashrates and efficiencies depending on how each chip tested. Only then do chips meet hashboards, boards meet enclosures, and units meet freight. When a vendor's announced miner slips a quarter, the delay usually lives somewhere in this pipeline, not in marketing.

After tape-out the design enters fabrication at the foundry, where the mask set is created and used to print the circuit onto wafers, which are then diced, packaged, binned, and finally soldered onto the hashboards that end up on your shelf or your repair bench.