ESD Protection

ESD protection is the set of on-chip structures — and the bench discipline surrounding them — that defends an integrated circuit from electrostatic discharge: sudden, high-voltage transfers of accumulated static charge. A spark you can barely feel sits at roughly 3,000 volts; discharges well below human perception can still destroy semiconductors, and an unprotected transistor gate whose oxide is mere nanometers thick will rupture instantly. On-chip protection works by placing clamps and diodes near every input, output, and power pad that stay dormant during normal operation but turn on within nanoseconds during a strike, shunting the discharge harmlessly to a supply or ground rail and steering current away from the delicate core circuitry.

The Models Engineers Design Against

Protection is qualified against standardized stress events. The Human Body Model (HBM) emulates a charged person — about 100 pF discharging through roughly 1.5 kΩ of body resistance — touching a pin, producing a pulse of several amps lasting on the order of 100 nanoseconds. The Charged Device Model (CDM) covers the opposite and increasingly dominant case: the packaged chip itself accumulates charge, then dumps it extremely fast when a pin contacts ground, with sub-nanosecond rise times that demand equally fast clamps. Parts carry HBM and CDM voltage ratings precisely so manufacturers and handlers know how much abuse the built-in protection absorbs — and the industry trend is sobering: as geometries shrink, intrinsic ratings fall, which shifts ever more of the burden onto how boards are handled outside the chip.

Latent Damage: The Failure You Do Not See

The cruelest ESD outcome is not the dead-on-arrival chip — it is the wounded one. A discharge too weak to kill can partially degrade a gate oxide or junction, leaving a part that passes every test today and fails in three weeks under thermal stress. On a hashboard this presents as the maddening intermittent: a chain that errors only when warm, a board that "fixed itself" after reflow and died again. Latent damage is why ESD discipline cannot be validated by whether the board still works afterward; by the time the symptom appears, the cause is weeks in the past and unprovable.

Bench Discipline for Mining Hardware

Repair benches, dry winter air, and bare-board handling are an ESD minefield — a hashboard or control board is most vulnerable exactly when it is out of its chassis for inspection or rework. The countermeasures are cheap and non-negotiable: a wrist strap with its megohm series resistor, worn and actually clipped to a grounded point; a dissipative mat bonded to the same ground; boards transported and stored in shielded bags, not bubble wrap; synthetic fleece nowhere near the bench. Dry air deserves special respect — relative humidity below about 30%, typical of heated northern workshops in winter, lets charge build to multiples of what the same movements generate in summer. Every board that arrives through our repair intake is handled under full ESD controls for precisely these reasons; the habit costs seconds and the alternative costs hashboards.

Last Line, Not Only Line

The on-chip clamps buy a margin of safety, but they are a last line of defense sized for brief qualification pulses, not for careless handling repeated daily. Treat the ratings as the chip's crash structure: good that it exists, better never to test it. ESD protection is invisible until the moment it saves a chip — or the moment its absence kills one weeks after the touch that did it. Read alongside latch-up, a related parasitic failure that an ESD event can trigger, and ground yourself before you ground a board.

Total cost of a compliant one-person bench — strap, mat, ground cord, a stock of shielded bags — is less than a single hashboard's shipping fee, which makes the economics the easiest part of the argument.