Definition
Latch-up is a destructive failure mode unique to CMOS in which an unintended low-impedance path forms directly between the power and ground rails. Every CMOS layout contains hidden parasitic bipolar transistors — a PNP and an NPN formed by the doping wells and junctions that make up the NMOS and PMOS devices. Together they create a PNPN structure electrically identical to a thyristor, or silicon-controlled rectifier (SCR). Under the right trigger, this parasitic SCR turns on, and once on it holds itself on.
How it goes wrong
If one parasitic transistor starts conducting, it feeds base current to the other, which feeds it back — a positive-feedback loop that latches the path into a hard short. Current floods from supply to ground, limited only by the rails themselves, and the device can overheat and suffer permanent damage within moments. The trigger is often a voltage transient, an overshoot on an I/O pin, or an ESD event that injects current into a well.
Prevention and the repair-bench angle
Designers fight latch-up by breaking the feedback gain below the threshold where it can sustain — surrounding transistors with isolation trenches or guard rings, adding well and substrate taps to lower parasitic resistance, and spacing devices apart. Some parts add detection circuitry that shuts down on a latch-up event. On the bench, latch-up explains a board that suddenly draws huge current and gets hot for no obvious reason; cutting power before the SCR cooks the silicon can sometimes save the chip, but prevention through clean power and careful handling is the real defense.
Latch-up is CMOS biting itself — a parasitic device the designer never wanted, waiting for a trigger. Read with ESD protection, a common trigger source, to see how transients turn into dead silicon.
In Simple Terms
Latch-up is a destructive failure mode unique to CMOS in which an unintended low-impedance path forms directly between the power and ground rails. Every CMOS…