ASIC Mining Chip Database

First-generation 28nm SHA-256 silicon. Long obsolete; no live cross-substitution path with any later chip.

Single-generation part; not mixed with later silicon.

Decade-old chips are sometimes re-marked and sold as a newer generation — verify the package, date code, and on-board chip count against this table before buying any "S5/S7-era" board.

The whole S9 family — including the S9 SE (BM1391) and S9j (BM1393) refinements — reports the same 0x1387 chip ID and speaks the identical BM1387 command/register surface. Those are silicon-binning / process-shrink variants, register-compatible with BM1387 for every wire-format purpose. (Verified: BM1391/BM1393-vs-BM1387 disambiguation, PR-054.)

S9-family chips are interchangeable at the protocol layer, but mixing dies of different bins on one board changes the achievable frequency/voltage envelope — keep a board single-bin.

The S9 was the most-cloned mining board in history. Re-balled and harvested BM1387 dies are common on the used market. Cross-check the 63-chip / 21-domain layout and the U3 PIC (PIC16F1704) before trusting a "refurbished" S9 board.

A 7nm refinement of the S9 line. The runtime keys it on the same 0x1387 chip ID and shares the BM1387 driver — it is register-compatible with BM1387, not a separate dispatch identity. The S15/T15 host attribution is the curated-reference consensus; some firmware corpus rows fold BM1391 under the S9 SE.

Register-compatible with the S9 family; do not mix BM1391 boards with BM1387 boards in one miner without re-confirming the per-model frequency table.

Less commonly cloned than BM1387, but the same caution applies — verify the chip ID readback and board geometry rather than trusting a silk-screen mark.

IMPORTANT: BM1393 is an inferred, named-only S9j-family refinement that reports the same 0x1387 chip ID and runs on the shared BM1387 driver — it is NOT the S17/T17 chip. The S17/T17 generation uses the 7nm BM1397 (see below). Older references that list "BM1393 = S17/T17" are incorrect; D-Central corrects that here. (Verified: PR-054 disambiguation; MASTER_CHIP_CATALOG; HARDWARE_REFERENCE.)

Treated by firmware as S9-family silicon (0x1387). Never wire a BM1393-marked board to an S17/T17 control board expecting it to enumerate.

Because "BM1393" is widely mis-documented as an S17 chip, mis-labelled boards circulate. Trust the chip-ID readback and the S9-family geometry, not the printed model name.

The ENTIRE S17/T17 base and "e" generation uses the 7nm BM1397 — 672 cores, 0x51/0x41 command-header family. It is the registered, production driver for 0x1397. (Verified: MASTER_CHIP_CATALOG L16, HARDWARE_REFERENCE, the BM1396/1397 disambiguation PR-056, the chip genealogy bible.)

BM1397 and BM1396 (the S17+/T17+ "Plus" chip) are register-compatible within the same 0x51/0x41 header family but are DISTINCT chip IDs — firmware dispatches on the GetAddress word and a 0x1396 die is never silently mapped onto the 0x1397 driver. Do not cross-populate boards between the base/e and the Plus generation.

BM1397 is one of the most-studied mining ASICs and is open-documented (Mujina). Harvested S17-era dies are heavily recycled — the S17 generation was notorious for thermal failures, so "tested working" BM1397 boards on the used market warrant a full bench check.

The "Plus" sibling of BM1397, hosting the S17+/T17+. It is register-compatible with BM1397 within the BM1397-era 0x51/0x41 header family but carries its own 0x1396 chip ID. (Verified: BM1396/1397 disambiguation PR-056; chip genealogy bible.)

Distinct identity from BM1397 — a 0x1396 die enumerates as its own chip and is never mapped onto the BM1397 driver. Keep S17+/T17+ boards on their own family; do not mix with base-S17 (BM1397) boards.

Frequently conflated with BM1397 in marketplace listings. Verify the chip-ID readback (0x1396 vs 0x1397) and the S17+/T17+ host attribution before swapping a board between platforms.

The S19 (76 chips, 2 chips/domain) and the S19 Pro (114 chips, 3 chips/domain) BOTH use BM1398 on a 38-domain board — the difference is chip population per domain, not a different chip. (Verified: HASHBOARD_DIAGNOSTICS §1.3; MASTER_CHIP_CATALOG.)

A genuine BM1398 board is dispatch-compatible, but an S19 board and an S19 Pro board are NOT interchangeable wholesale — they differ in chip population, domain wiring, and boost topology. Match the board to the model.

The S19 line is the most-traded used ASIC; harvested BM1398 dies and re-worked boards are everywhere. Confirm the 76- vs 114-chip layout and the dsPIC33EP voltage controller before paying for a "Pro".

Bitmain's first 5nm SHA-256 die, used in the S19j Pro / S19j Pro+. A distinct 0x1362 chip ID with its own registered driver. (Verified: MASTER_CHIP_CATALOG — DRIVEN, S19j Pro 66 TH/s sustained on the bench.)

Not interchangeable with the 7nm BM1398 S19 boards despite the shared "S19" badge — different node, different chip ID, different board. Match the board to the exact S19j Pro revision.

The "S19j Pro" badge spans both 7nm and 5nm silicon depending on revision; verify the chip-ID readback rather than the model sticker.

Bitmain's first 5nm flagship die (S19 XP). The single-chip variant is the heart of the Bitaxe Ultra and one chip per cell in the Bitaxe Hex Supra — proving a full-Antminer ASIC can drive a sovereign solo miner. (Verified: bible-facts; MASTER_CHIP_CATALOG — first share on a Bitaxe-class board 2026-03-19.)

In a Bitaxe Ultra it runs as a single chip on its own board; in an Antminer XP board it is daisy-chained. Do not transplant an XP-harvested die into a Bitaxe board — package and board design differ.

On the Bitaxe side, clone boards using questionable BM1366 sourcing exist. On the Antminer side, the XP is a premium target for re-marked dies. In both cases, verify the chip ID and source provenance.

A major architectural shift: ~6-7x per-chip hashrate, ~1.2 V domains (up from ~0.4 V), and NO PIC controller (removed this generation). The single-chip variant powers the Bitaxe Supra. (Verified: HASHBOARD_DIAGNOSTICS §1.3 — 108 chips / 12 domains / no PIC; KNOWN-BASELINE — Supra=BM1368.)

S21 (BM1368) and S21 XP / Pro (BM1370) are different 5nm chips on different boards — same family badge, distinct chip IDs (0x1368 vs 0x1370). Never cross-populate. S21 boards have no PIC, so never GPIO-reset them like an S9/S19 — probe the voltage controller instead.

The S21 is the current high-value target. Because it carries no PIC, a "missing PIC" is normal, not a defect — counterfeit listings sometimes claim the opposite. Verify the 108-chip / 12-domain layout and the CV1835 control board.

Bitmain's most efficient SHA-256 die to date (15 J/TH). The single-chip variant is the BM1370 in the Bitaxe Gamma and Gamma Turbo — the highest-efficiency open-source solo board you can buy. (Verified across 15+ Bible docs: Gamma=BM1370, the protected mapping; HASHBOARD_DIAGNOSTICS §1.3 — S21 XP 91 chips / 13 domains.)

Distinct from BM1368 (S21 base) — 0x1370 vs 0x1368, different board geometry. Same NoPIC, audio-DAC-controlled voltage architecture as the S21; probe the controller, never GPIO-reset.

On Bitaxe boards, the Gamma chip is the most-counterfeited single die — re-marked or salvaged silicon shows up on the cheapest "Gamma" clones. Verify the chip-ID readback (0x1370) and buy from a documented source; the genuine Gamma is BM1370, never BM1371 or any other invented part number.

RUMORED / PRE-COVERAGE: BM1373 is the projected S23-generation die. Every value here is a placeholder pending hardware — D-Central publishes it with confirmed-vs-rumored discipline. A 0x1373 scaffold exists; no live silicon. (Verified-as-projected: MASTER_CHIP_CATALOG — NAMED ONLY, internal intel 2026-04-14.)

No production hardware to substitute or pair-bond yet. This row will be updated to confirmed values once a unit reaches the bench.

No genuine BM1373 hardware is on the open market. Treat any "S23 in stock" listing as unverified until Bitmain ships.

A Scrypt (not SHA-256) ASIC — not interchangeable with any Bitcoin miner chip. Listed for completeness. (Verified: MASTER_CHIP_CATALOG §2; HASHBOARD_DIAGNOSTICS §2.2 — 72 chips / 12 domains.)

Scrypt-only; never cross-populate with a SHA-256 board.

Aging L3+ stock is frequently re-sold; verify the 72-chip Scrypt layout.

The 7nm Scrypt die behind the L7 (nameplate 9.5 GH/s @ 3,425 W). Scrypt-only — no SHA-256 substitution path. (Verified: MASTER_CHIP_CATALOG §2 — silicon profile, 120 chips/chain × 4 chains.)

Scrypt-only; not interchangeable with Bitcoin silicon.

High-value Scrypt part; verify the 4-chain / 120-chip-per-chain layout.

MicroBT identifies its silicon by a cgminer chip_id rather than a public part number. K1 (0x1000) is the legacy 28nm generation. Cores-per-chip is a documented GAP — MicroBT stores chips-per-board (chip_num), not cores-per-chip. (Verified: MASTER_CHIP_CATALOG §3 — NAMED ONLY, cgminer.default chip_id.)

WhatsMiner boards are tied to their model's firmware and chip_id; do not cross-populate across K-generations.

MicroBT does not publish chip part numbers, so "chip type" claims on used WhatsMiner boards are unverifiable by marking alone — confirm the model and firmware chip_id.

The 16nm K-Gen-2 family. chip_id 0x1800 is read from the stock cgminer config; the part number is not published by MicroBT. (Verified: MASTER_CHIP_CATALOG §3 — cgminer.default.m10s chip_id 0x1800.)

Match the board to its M-series model and firmware; chip_id must agree with the configured model.

Verify by model + firmware chip_id, not by any silk-screen part number.

The 7nm K-Gen-3 family (with a newer 5nm/3nm M50/M60 extension). chip_id 0x1920 from the M20S stock config; M20S stores chip_num = 105 (chips per board), not cores per chip. (Verified: MASTER_CHIP_CATALOG §3 — cgminer.default.m20s chip_id 0x1920; M60S model_code 0x3C45B000.)

Do not mix M19/M20-class boards with M50/M60-class boards; the chip generation and firmware differ.

High-value modern WhatsMiner boards are cloned; verify model + firmware chip_id and board chip_num.

Canaan Avalon chips are identified per model; the freq/voltage tables are ENCRYPTED on-device (AES-CBC, single industrial master key, OTP on a K210 eFuse) — so per-chip tuning data is not publicly recoverable. (Verified: MASTER_CHIP_CATALOG §4 — NAMED ONLY; AVALON encrypted-payload finding.)

Avalon boards are matched to their MM-series control module (MM317/318/319); do not cross-populate across MM generations.

Canaan does not publish chip part numbers; verify by model + MM firmware version.

The A14-series Avalon die family (MM318_X2 firmware). Freq/voltage tables encrypted on-device. (Verified: MASTER_CHIP_CATALOG §4 — NAMED ONLY.)

Match to the MM318 control module and cooling type (air vs liquid).

Verify by model + MM318 firmware, not by chip marking.

The current 5nm-class A15-series Avalon die family (MM319 firmware). Freq/voltage tables encrypted on-device. (Verified: MASTER_CHIP_CATALOG §4 — NAMED ONLY.)

Match to the MM319 control module and cooling type.

Verify by model + MM319 firmware version.