ASIC Hashboard Architecture Reference

Quick answer

This matrix maps 15 Bitmain Antminer models (SHA-256 and Scrypt) to the physical build of their hash board — one row per model: ASIC chip, chips per board, boards per unit, total chips, voltage DOMAINS per board, chips per domain, the per-DOMAIN rail voltage (NOT per-chip — per-chip equals the domain rail divided by chips-per-domain), boost output, PIC presence and reference designator, EEPROM refdes, temperature-sensor count, crystal, stock PSU, level shifters and the common chain-break signature. For example an Antminer S19 carries 76 BM1398 chips across 3 boards (228 total) in 38 domains of 2 chips at ~0.36V per domain, PIC U3, EEPROM U5; an S21 carries 108 BM1368 chips in 12 domains of 9 chips at ~1.2V per domain with no PIC.

Use it to identify a board before you diagnose or order parts. Free CSV/JSON under CC BY 4.0. Component reference designators vary by board revision — verify against the specific board. Voltage figures are per voltage domain, never per chip.

Architecture diagrams

Three hand-drawn, text-described diagrams of how these boards are actually built — the S19 signal chain and chain-break behaviour, the per-domain voltage ladder, and how the S19 and S21 boards differ. Full data for every model is in the matrix below.

Figure 1. The S19 signal chain. A control board drives three identical hash boards (Chain 0–2) over 18-pin ribbon cables; each board is 76 BM1398 ASICs in 38 voltage domains of two chips (~0.36 V per domain). Inside a chain, commands, the 25 MHz clock and reset propagate forward chip-to-chip (CI→CO) while nonce responses travel back in reverse (RO→RI). The PIC (U3) and EEPROM (U5) sit on an I2C side bus, not the hash path. A single dead chip breaks both the series power string and the signal chain at once, so every chip downstream vanishes and the controller reports far fewer ASICs than the board actually carries. Source: D-Central Mining Bible, HASHBOARD_DIAGNOSTICS.

Figure 2. The S19 power-domain ladder. The PSU delivers 12–15 V, a boost converter raises it to a 19 V rail, and that rail feeds a dedicated DC-DC converter for each of the 38 voltage domains. The two BM1398 chips inside a domain are wired in series, so the domain regulates to ~0.36 V and the 38 domains stack to ≈ 13.68 V across the string. Critically, that ~0.36 V is a per-domain figure — the value you measure on the bench spans the whole domain, not one chip. Per-chip core voltage is the domain rail divided by chips-per-domain (≈ 0.18 V here) and is never probed directly. Source: D-Central Mining Bible, HASHBOARD_DIAGNOSTICS.

Figure 3. S19 versus S21 board architecture at a glance. The bar strips make the trade-off visible: the S19 (BM1398) spreads 76 chips across 38 narrow voltage domains of 2 chips (~0.36 V each), while the S21 (BM1368) packs 108 chips into just 12 wide domains of 9 chips (~1.2 V each). The other field to note is the PIC calibration controller: present on S19-class boards as U3, but removed entirely in the BM1368 generation — so an S21 board has no PIC to reprogram. Source: D-Central Mining Bible, HASHBOARD_DIAGNOSTICS + ANTMINER_ARCHITECTURE.

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Antminer S9 BM1387

S9 (BM1387 generation) · Bitmain

Chips per board	63
Boards per unit	3
Total chips per unit	189
Voltage domains/board	21
Chips per domain	3
Per-DOMAIN rail (V)	0.40
Boost output (V)	unverified (no discrete boost stage documented; the 21 domains stack in series to ~8.4V from the ~12V PSU rail)
PIC present	yes
PIC refdes	unverified (per-board PIC addressed on I2C at 0x50 + (chain−1); S9 uses chains 6/7/8)
EEPROM refdes	unverified (no EEPROM populated on the live-probed S9 at 0x50–0x54)
Temp sensors	unverified
Crystal	25 MHz
Stock PSU	APW3++ / APW7
Level shifters	yes (3.3V↔chip-level UART; count unverified)

Chain-break signature: Fixture reports fewer than 63 chips on a chain; the break is the chip immediately after the last detected chip (a dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO, so every chip downstream goes invisible).

Confidence: high on chip/domain/PSU; medium overall (board-level refdes not enumerated for S9 in the Bible)

Source: HASHBOARD_DIAGNOSTICS.md §1.2, §2.2, §3.5; ANTMINER_ARCHITECTURE.md (S9 I2C / control board)

Antminer S9k / S9 SE BM1387

S9 refresh (BM1387 generation) · Bitmain

Chips per board	60
Boards per unit	3
Total chips per unit	180
Voltage domains/board	6
Chips per domain	10
Per-DOMAIN rail (V)	1.60
Boost output (V)	unverified (no discrete boost stage documented; the 6 domains stack in series to ~9.6V from the ~12V PSU rail)
PIC present	yes
PIC refdes	unverified (PIC removed only at the BM1368/S21 generation, so the BM1387 board still carries one; refdes not enumerated)
EEPROM refdes	unverified
Temp sensors	unverified
Crystal	25 MHz (Y1)
Stock PSU	APW3 / APW3++
Level shifters	yes (3.3V↔chip-level UART at the board interface; cross-domain shifters arrived at the S21 generation; count unverified)

Chain-break signature: Fixture reports fewer than 60 chips on a chain; the break is the chip immediately after the last detected chip (a dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO, so every chip downstream goes invisible).

Confidence: high on chip/domain structure and PSU — the Bible lists the S9k/S9SE board explicitly: 60 chips in 6 domains of 10, a different layout from the classic S9 (63 chips, 21×3); medium on component refdes (not enumerated)

Source: HASHBOARD_DIAGNOSTICS.md §1.2, §2.2, §3.4, §3.5; PSU_PROTOCOL_BIBLE.md §1 (APW3/APW3++ → S9k/S9 SE)

Antminer S15 BM1391

S15 (BM1391 generation) · Bitmain

Chips per board	72
Boards per unit	3
Total chips per unit	216
Voltage domains/board	12
Chips per domain	6
Per-DOMAIN rail (V)	1.53
Boost output (V)	unverified (APW8 supplies 16.32–20.04V directly; the ~18.36V domain stack runs off the PSU rail — no discrete boost stage documented)
PIC present	yes
PIC refdes	unverified (PIC removed only at the BM1368/S21 generation, so the BM1391 board still carries one; refdes not enumerated)
EEPROM refdes	unverified
Temp sensors	unverified
Crystal	25 MHz (Y1)
Stock PSU	APW8 (16–20V)
Level shifters	yes (3.3V↔chip-level UART at the board interface; cross-domain shifters arrived at the S21 generation; count unverified)

Chain-break signature: Fixture reports fewer than 72 chips on a chain; the break is the chip immediately after the last detected chip (a dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO; all downstream chips go invisible).

Confidence: high on chip/domain structure and PSU (Bible §1.2 + §2.2); medium on component refdes (not enumerated)

Source: HASHBOARD_DIAGNOSTICS.md §1.2, §2.2, §3.4, §3.5; PSU_PROTOCOL_BIBLE.md §1 (APW8 16–20V → S15/T15)

Antminer T15 BM1391

T15 (BM1391 generation) · Bitmain

Chips per board	72
Boards per unit	3
Total chips per unit	216
Voltage domains/board	12
Chips per domain	6
Per-DOMAIN rail (V)	1.65
Boost output (V)	unverified (APW8 supplies 16.32–20.04V directly; the ~19.8V domain stack runs off the PSU rail — no discrete boost stage documented)
PIC present	yes
PIC refdes	unverified (PIC removed only at the BM1368/S21 generation, so the BM1391 board still carries one; refdes not enumerated)
EEPROM refdes	unverified
Temp sensors	unverified
Crystal	25 MHz (Y1)
Stock PSU	APW8 (16–20V)
Level shifters	yes (3.3V↔chip-level UART at the board interface; cross-domain shifters arrived at the S21 generation; count unverified)

Confidence: high on chip/domain structure and PSU (Bible §1.2 + §2.2 — same 72-chip/12-domain BM1391 board as the S15, run at a higher 1.65V domain rail); medium on component refdes (not enumerated)

Source: HASHBOARD_DIAGNOSTICS.md §1.2, §2.2, §3.4, §3.5; PSU_PROTOCOL_BIBLE.md §1 (APW8 16–20V → S15/T15)

Antminer S17 / T17 BM1397

S17 / T17 (BM1397 generation) · Bitmain

Chips per board	48
Boards per unit	3
Total chips per unit	144
Voltage domains/board	12
Chips per domain	4
Per-DOMAIN rail (V)	1.55
Boost output (V)	unverified (APW9 supplies 14.5–21V directly; the ~18.5V domain stack may run without a discrete boost)
PIC present	yes
PIC refdes	unverified (PIC was removed only at the BM1368/S21 generation, so the BM1397 board still carries one; refdes not enumerated in the Bible)
EEPROM refdes	unverified
Temp sensors	unverified
Crystal	25 MHz
Stock PSU	APW9
Level shifters	yes (count unverified)

Chain-break signature: Fixture reports fewer than 48 chips on a chain; the break is the chip immediately after the last detected chip (open/short chip stops forwarding the daisy-chain signals; all downstream chips go invisible).

Confidence: medium. The entire S17/T17 generation (S17, S17 Pro, T17) uses the 7nm BM1397 — NOT BM1393, which is a named-only inferred S9j variant (bible-facts.md error #9, corrected 2026-06-12). Board figures are the Bible S17 reference; the T17 shares the platform but its model-specific chip count is not separately enumerated.

Source: HASHBOARD_DIAGNOSTICS.md §1.2, §2.2, §3.5; PSU_PROTOCOL_BIBLE.md §1 (APW9 → S17/S17 Pro/T17)

Antminer S17+ / T17+ BM1397

S17+ (BM1397 generation) · Bitmain

Chips per board	48
Boards per unit	3
Total chips per unit	144
Voltage domains/board	12
Chips per domain	4
Per-DOMAIN rail (V)	unverified (the sibling S17 BM1397 board runs 1.55V per domain; the BM1397 board rail is not separately enumerated in the Bible)
Boost output (V)	unverified (APW9+ supplies 14.5–21V directly; no discrete boost stage documented)
PIC present	yes
PIC refdes	unverified (PIC removed only at the BM1368/S21 generation, so the BM1397 board still carries one; refdes not enumerated)
EEPROM refdes	unverified
Temp sensors	unverified
Crystal	25 MHz (Y1)
Stock PSU	APW9+
Level shifters	yes (3.3V↔chip-level UART at the board interface; cross-domain shifters arrived at the S21 generation; count unverified)

Chain-break signature: Fixture reports fewer than 48 chips on a chain; the break is the chip immediately after the last detected chip (a dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO; all downstream chips go invisible).

Confidence: medium-high. 48 chips/board is the Bible's S17+ power-profile census (3 chains × 48); 12 domains is the Bible's BM1397 chip-generation figure; chips-per-domain is the exact division of the two (48 ÷ 12 = 4). The T17+ shares the BM1397 platform but its chip count is not separately enumerated in the Bible.

Source: HASHBOARD_DIAGNOSTICS.md §1.2 (BM1397 → S17/S17 Pro/T17/S17+/T17+, 12 domains; the S17e/T17e are BM1396), §3.4, §3.5; POWER_PROFILES_CATALOG.md §3.2 (S17+ = 3 chains × 48 chips); PSU_PROTOCOL_BIBLE.md §1 (APW9+ → S17+/S17e/T17+/T17e)

Antminer S19 BM1398

S19 (BM1398 generation) · Bitmain

Chips per board	76
Boards per unit	3
Total chips per unit	228
Voltage domains/board	38
Chips per domain	2
Per-DOMAIN rail (V)	0.36
Boost output (V)	19 (14V boost input → 19V; LDO chain 19V → 1.8V → 0.8V per domain)
PIC present	yes
PIC refdes	U3 (PIC16F1704)
EEPROM refdes	U5
Temp sensors	4 (U4, U6, U7, U8)
Crystal	25 MHz (Y1)
Stock PSU	APW12
Level shifters	U1, U2 (2)

Chain-break signature: Fixture reports fewer than 76 chips on a chain; the break is the chip immediately after the last detected chip (e.g. 29 of 76 detected → fault at chip 30). A dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO.

Confidence: high

Source: HASHBOARD_DIAGNOSTICS.md §1.3, §2.2, §3.5, §12.1

Antminer S19 Pro BM1398

S19 (BM1398 generation) · Bitmain

Chips per board	114
Boards per unit	3
Total chips per unit	342
Voltage domains/board	38
Chips per domain	3
Per-DOMAIN rail (V)	0.32
Boost output (V)	20 (12.6V → 20V via Q9; domains 38–32 LDO off the 19V boost, domains 31–1 LDO off VDD12.6V → 1.8V)
PIC present	yes
PIC refdes	U6 (PIC16F1704)
EEPROM refdes	U10
Temp sensors	4 (U5, U7, U8, U9)
Crystal	25 MHz (Y1)
Stock PSU	APW12
Level shifters	U1, U2 (2)

Chain-break signature: Fixture reports fewer than 114 chips on a chain; the break is the chip immediately after the last detected chip. A dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO; all downstream chips go invisible.

Confidence: high

Source: HASHBOARD_DIAGNOSTICS.md §1.3, §2.2, §3.5, §12.1

Antminer S19j Pro BM1362

S19j (BM1362) · Bitmain

Chips per board	126
Boards per unit	3
Total chips per unit	378
Voltage domains/board	42
Chips per domain	3
Per-DOMAIN rail (V)	0.30
Boost output (V)	19
PIC present	yes
PIC refdes	unverified (present per §12.1; refdes not enumerated)
EEPROM refdes	unverified (present per §12.1; refdes not enumerated)
Temp sensors	4 (refdes not enumerated)
Crystal	25 MHz (Y1)
Stock PSU	APW12
Level shifters	U1, U2 (2)

Chain-break signature: Fixture reports fewer than 126 chips on a chain; the break is the chip immediately after the last detected chip. A dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO.

Confidence: high on counts; medium on refdes

Source: EEPROM_TEMPLATE_ATLAS.md (BHB426xx=BM1362, firmware-verified) + HASHBOARD_DIAGNOSTICS.md §1.2, §2.2, §3.5, §12.1

Antminer S19 XP BM1366

S19 XP (BM1366 generation) · Bitmain

Chips per board	110
Boards per unit	3
Total chips per unit	330
Voltage domains/board	11
Chips per domain	10
Per-DOMAIN rail (V)	~0.4
Boost output (V)	19
PIC present	yes
PIC refdes	unverified (PIC microcontroller present as I2C slave managing the regulators; refdes not enumerated)
EEPROM refdes	unverified (EEPROM present, stores board identity; refdes not enumerated)
Temp sensors	unverified (TMP75 I2C temp sensor present; exact count not enumerated, §12.1 notes 2+ sensors)
Crystal	25 MHz (Y1)
Stock PSU	APW12 / APW171215
Level shifters	yes (3.3V↔1.8V for UART; count unverified)

Chain-break signature: Fixture reports fewer than 110 chips on a chain; the break is the chip immediately after the last detected chip. A dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO; all downstream chips go invisible.

Confidence: medium. Domain count 11 × 10 chips/domain is from ANTMINER_ARCHITECTURE (S19 XP hash board); HASHBOARD_DIAGNOSTICS §12.1 lists the S19 XP domain split as 'Varies'.

Source: ANTMINER_ARCHITECTURE.md (S19 XP Hash Board); HASHBOARD_DIAGNOSTICS.md §1.2, §3.5, §12.1

Antminer S21 / T21 BM1368

S21 (BM1368 generation) · Bitmain

Chips per board	108
Boards per unit	3
Total chips per unit	324
Voltage domains/board	12
Chips per domain	9
Per-DOMAIN rail (V)	~1.2
Boost output (V)	~25 (VDD_IN → ~25V via U206; domains 1–10 use 3 LDOs each to 1.2V/0.8V, domains 11–12 use MP2019 bucks U166/U200 → 2V → LDOs)
PIC present	no
PIC refdes	n/a (PIC removed at the BM1368 generation)
EEPROM refdes	U6
Temp sensors	2 (U5 inlet, U7 outlet)
Crystal	25 MHz (Y1)
Stock PSU	APW171215a
Level shifters	11 units

Chain-break signature: Fixture reports fewer than 108 chips on a chain (e.g. 29 of 108 detected → fault at chip 30). A dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO; all downstream chips go invisible.

Confidence: high. Figures are the Bible's S21/T21 BM1368 reference; the T21 shares the BM1368 hash-board platform.

Source: HASHBOARD_DIAGNOSTICS.md §1.3, §2.2, §3.5, §12.2; ANTMINER_ARCHITECTURE.md (S21 hash board)

Antminer S21 Pro BM1370

S21 (BM1370 generation) · Bitmain

Chips per board	unverified (§12.2 lists 'Varies')
Boards per unit	3
Total chips per unit	unverified
Voltage domains/board	unverified (§12.2 lists 'Varies')
Chips per domain	unverified (§12.2 lists 'Varies')
Per-DOMAIN rail (V)	~1.0
Boost output (V)	~21
PIC present	no
PIC refdes	n/a (PIC removed at the BM1368/BM1370 generation)
EEPROM refdes	unverified (EEPROM present; refdes not enumerated)
Temp sensors	unverified (multiple sensors; count not enumerated)
Crystal	25 MHz (Y1)
Stock PSU	APW171215a
Level shifters	12+ units

Chain-break signature: Fixture reports fewer chips than the chain expects; the break is the chip immediately after the last detected chip. A dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO.

Confidence: medium-low. The Bible records the S21 Pro chip/domain counts as 'Varies'; per-domain rail ~1.0V, boost ~21V and the BM1370 chip are grounded.

Source: HASHBOARD_DIAGNOSTICS.md §1.2, §3.5, §12.2

Antminer S21 XP BM1370

S21 XP (BM1370 generation) · Bitmain

Chips per board	91
Boards per unit	3
Total chips per unit	273
Voltage domains/board	13
Chips per domain	7
Per-DOMAIN rail (V)	~1.04
Boost output (V)	~21 (domains 1–11 use 1.2V/0.8V LDOs ×3 per domain, domains 12–13 use MP2019 bucks U146/U202 → 2.5V → LDOs)
PIC present	no
PIC refdes	n/a (PIC removed at the BM1368/BM1370 generation)
EEPROM refdes	unverified (EEPROM present; refdes not enumerated)
Temp sensors	unverified (U19 4-way I2C switch; U20, U22 isolation ICs — discrete temp-sensor count not enumerated)
Crystal	25 MHz (Y1)
Stock PSU	APW171215a
Level shifters	12 (U1–U12)

Chain-break signature: Fixture reports fewer than 91 chips on a chain; the break is the chip immediately after the last detected chip. A dead/open chip stops forwarding CI/CO, CLK, RST and BI/BO; all downstream chips go invisible.

Confidence: high

Source: HASHBOARD_DIAGNOSTICS.md §1.3, §2.2, §3.5, §12.2; ANTMINER_ARCHITECTURE.md (S21 XP hash board)

Antminer L3+ BM1485

L3+ (BM1485, Scrypt/Litecoin) · Bitmain

Chips per board	72
Boards per unit	4
Total chips per unit	288
Voltage domains/board	12
Chips per domain	6
Per-DOMAIN rail (V)	0.80
Boost output (V)	unverified (no discrete boost stage documented; the 12 domains stack in series to ~9.6V from the ~12V PSU rail)
PIC present	yes
PIC refdes	unverified (PIC16F1704, one per hashboard at I2C 0x55 per the BM1485 protocol bible — same family as the S9; the stock init path drives chain reset/plug-detect via BeagleBone GPIO; refdes not enumerated)
EEPROM refdes	unverified (hashboard identity EEPROM at I2C 0x50, one per chain; refdes not enumerated)
Temp sensors	unverified
Crystal	25 MHz (the BM1485 baud/PLL reference clock; board refdes not enumerated)
Stock PSU	APW7
Level shifters	yes (the RST chain passes through a level shifter from the BeagleBone control board; count unverified)

Chain-break signature: Fixture reports fewer than 72 chips on a chain; the break is the chip immediately after the last detected chip (a dead/open chip stops forwarding the daisy-chain signals; all downstream chips go invisible). Note: the L3+ runs 4 hash boards, not 3.

Confidence: high on chip/domain structure, board count and PSU (Bible §2.2 + the BM1485 protocol bible, source-verified); medium on component refdes (not enumerated)

Source: HASHBOARD_DIAGNOSTICS.md §2.2, §3.5; BM1485 protocol bible (L3+ = BeagleBone Black + 4 hashboards × 72 BM1485; PIC16F1704 @ I2C 0x55; core 0.6–0.8V); PSU_PROTOCOL_BIBLE.md §1 (APW7 → L3+)

Antminer L7 BM1489

L7 (BM1489, Scrypt/Litecoin) · Bitmain

Chips per board	120
Boards per unit	4
Total chips per unit	480
Voltage domains/board	unverified (domain split not enumerated in the Bible for the L7)
Chips per domain	unverified
Per-DOMAIN rail (V)	unverified (BM1489 core runs ~0.6V per the Bible — lower than the BM1485's 0.8V on its newer process; the board's domain rail is not enumerated)
Boost output (V)	unverified
PIC present	unverified (the Bible lists the L7 hashboard controller as TBD — a different scheme from the S9-family PIC; the control board is Zynq-based)
PIC refdes	unverified
EEPROM refdes	unverified (hashboard identity EEPROM at I2C 0x50 carrying BHB285xx/286xx/287xx board templates, firmware-verified; refdes not enumerated)
Temp sensors	unverified
Crystal	dual 25 MHz crystals — Y1 (chips 1–60), Y2 (chips 61–120)
Stock PSU	APW12 (1417, 14–17V)
Level shifters	unverified

Chain-break signature: Fixture reports fewer than 120 chips on a chain; the break is the chip immediately after the last detected chip. Note: the L7 runs 4 hash boards, not 3, and each chain is clocked by dual crystals (Y1 drives chips 1–60, Y2 drives chips 61–120).

Confidence: high on chip identity, chip/board counts, crystals and PSU (firmware-verified); low on the electrical topology (domain structure not enumerated in the Bible)

Source: HASHBOARD_DIAGNOSTICS.md §3.4 (L7 dual crystals), §3.5; BM1485/BM1489 protocol bible (L7 = Zynq + 4 hashboards × 120 BM1489, core ~0.6V); MASTER_CHIP_CATALOG.md + EEPROM_TEMPLATE_ATLAS.md (BM1489, BHB28xxx identity, firmware-verified); PSU_PROTOCOL_BIBLE.md §1 (APW12 1417 → L7)

Voltage is per voltage domain, never per chip (per-chip = domain rail ÷ chips-per-domain). Grounded in the D-Central Mining Bible (HASHBOARD_DIAGNOSTICS, ANTMINER_ARCHITECTURE, PSU_PROTOCOL_BIBLE) — a reference, not a guarantee; reference designators vary by board revision. Pairs with the ASIC chip reference, the ASIC chip spec cards, the power & connector pinout reference and the model hubs (S21, S19, S23). Got a dead board? Start a repair →

Identify your board. Decode the BHB part number silk-screened on your Antminer hash board — ASIC chip, board revision and the models it fits — with the Antminer hashboard part-number decoder.

Related products, repair, and setup paths

Last reviewed June 23, 2026.