ASIC Power & Connector Pinout Reference

Pin reference for the standard connectors on Bitcoin ASIC miners — PSU output terminals, the APW12/APW9 4-pin I2C signal terminal, the 18-pin hash-board signal cable, the chassis fan header and the control-board UART debug header. Each connector lists pin, signal, voltage and notes, grounded in the D-Central Mining Bible.

Quick answer

This reference maps 7 standard Bitcoin ASIC miner connectors pin-by-pin (27 documented pins): the Bitmain APW12/APW9 4-pin I2C signal terminal (J15: SDA, SCL, EN active-low, GND), the APW12 power outputs (J3/J4 OUT1 12–15V hash-board rail up to 233A, J6 OUT2 fixed 12V, J31 internal fan), the 18-pin control-board-to-hash-board signal cable (GND, 3.3V logic, RST, I2C temp/EEPROM, UART TX/RX), the chassis 4-pin fan header (GND, +12V, tachometer, PWM), and the control-board UART debug header (115200 8N1, 3.3V).

Use it to identify a connector before you wire, probe or repair. Free CSV/JSON under CC BY 4.0. Pin numbering and keying vary by board revision — always verify pin 1 against your specific board, and never hot-plug a signal cable while power is applied.

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APW12 J15 — 4-pin signal / voltage-control terminal signal/control

Applies to: APW12 (S19, S19 Pro, S19j, S19j Pro, T19). APW9/APW9+ expose the same PIC16F1704 I2C interface; APW17 is assumed identical (model string 'APW17_') but not independently verified in the Bible.

Pin	Signal	Voltage	Notes
1	SDA	3.3V	I2C data line (open-drain, external pull-ups)
2	SCL	3.3V	I2C clock line (open-drain)
3	EN	3.3V logic	Enable — ACTIVE LOW; pull to GND to enable PSU output
4	GND	0V	Ground reference

I2C bus runs at ~400 Hz (not kHz) on slave address 0x10. With EN shorted to GND and no I2C master attached, the output defaults to ~15.2V — firmware must set the correct target voltage before loading the hash boards. Never hot-plug this signal cable; the 3.3V logic can be damaged.

Source: PSU_PROTOCOL_BIBLE.md §2 (APW12 Physical Interface) · last verified 2026-06

APW12 J3/J4 — OUT1 high-current DC output power

Applies to: APW12 (S19 family). APW9/APW9+/APW17 provide an equivalent high-current hash-board output. Voltage is model-dependent: 12–15V on the S19-family APW12-1215; up to 14–17V on the APW12-1417 variant (L7/KA3).

Pin	Signal	Voltage	Notes
J3/J4 (+)	OUT1 +12–15V DC	12–15V (tunable)	Hash-board power. Up to 233A via multiple parallel pins / copper bus bars. Voltage is set through the J15 I2C control (8-bit DAC).
J3/J4 (−)	GND / return	0V	High-current return

Main hash-board power rail. Connection order (physical): connect negative (GND) first, then positive (+12V), and insert the signal cable LAST. Reverse on removal. Never connect/disconnect the signal cable while power is applied.

Source: PSU_PROTOCOL_BIBLE.md §2, §13 · last verified 2026-06

APW12 J6 — OUT2 control-board / auxiliary 12V output power

Applies to: APW12 family (control board + chassis fans).

Pin	Signal	Voltage	Notes
J6 (+)	OUT2 +12V	12V fixed	15A max; powers the control board and chassis fans
J6 (−)	GND / return	0V	Return

Fixed 12V auxiliary rail, independent of the tunable OUT1. Comes up first at power-on (~1–2s) to boot the control board before the hash boards are energised.

Source: PSU_PROTOCOL_BIBLE.md §1 (Internal Architecture), §2 · last verified 2026-06

APW12 J31 — internal PSU fan power fan (PSU internal)

Applies to: APW12 PSU internal cooling fan.

Pin	Signal	Voltage	Notes
J31 (+)	+12V (auxiliary rail)	12V	PSU internal cooling fan power
J31 (−)	GND	0V	Return

Fed from the internal auxiliary 12V rail. The PSU fan is governed by the PSU's own internal PIC/PWM thermal circuitry — it is NOT exposed on the I2C interface and cannot be overridden by the control board.

Source: PSU_PROTOCOL_BIBLE.md §11 (Fan Control) · last verified 2026-06

Hash-board IO connector — 18-pin signal cable (control board ↔ hash board) signal/data

Applies to: S19 / S21 generation (pin assignments confirmed across S19/S21 documentation). Numbering varies slightly by model generation — always verify against the specific board schematic.

Pin	Signal	Voltage	Notes
1	GND	0V	Ground reference
2	VCC_3V3	3.3V	Logic power from control board (CB→HB)
3	RST	0–3.3V	Reset to the chip chain (CB→HB)
4	SDA (I2C)	3.3V	Temp-sensor / EEPROM data (bidirectional)
5	SCL (I2C)	3.3V	Temp-sensor / EEPROM clock (CB→HB)
6	GND	0V	Ground
7	TX / CI	3.3V	UART transmit — command input (CB→HB)
8	RX / RO	3.3V	UART receive — response output (HB→CB)
9–18	Various	—	Additional GND, VCC and status signals — verify against board schematic

Carries power (3.3V), ground and the digital chain signals (CLK, CI/RO, RST, temp-sensor I2C). On the hash board, the 3.3V UART is level-shifted down to the chips' signal levels (~1.1V on S21, up to ~1.8V on S19). Insert this cable LAST and remove it FIRST — the 3.3V signals are damaged by hot-plugging.

Source: HASHBOARD_DIAGNOSTICS.md §1.4 (IO Connector Pinout) + ANTMINER_ARCHITECTURE.md · last verified 2026-06

Chassis cooling fan header — 4-pin fan (chassis)

Applies to: Antminer control-board fan headers (S9/S17/S19/S21 generations). Repair fixtures accept KF2510 4/6-pin and 5557 4-pin fan connectors.

Pin	Signal	Voltage	Notes
1	GND	0V	Ground
2	+12V	12V	Fan power (from the OUT2 auxiliary rail)
3	TACH (sense)	open-collector pulse	Tachometer — fan-speed feedback to the control board
4	PWM (control)	logic duty-cycle	Speed-control input from the control board

Standard 4-wire DC fan signals: GND, +12V, tachometer (RPM sense) and PWM speed control. Chassis fans are driven by the CONTROL BOARD, not the PSU (Zynq: FPGA PWM timer — register 0x0084 sets duty, 0x0004 reads RPM; Amlogic: SoC PWM channels 0,1), targeting hash-board TMP75 temperatures. The Bible enumerates these four signals but not their connector position — the pin numbering here follows the standard 4-wire DC-fan convention; confirm pin 1 keying on your specific board before wiring.

Source: HASHBOARD_DIAGNOSTICS.md §11.4–§11.5 + PSU_PROTOCOL_BIBLE.md §11 (Miner Chassis Fans) · last verified 2026-06

Control-board UART debug header signal (debug)

Applies to: Antminer control boards (Zynq and Amlogic generations). Used with a USB-to-TTL adapter (CP2102 / CH340) for serial diagnostics.

Pin	Signal	Voltage	Notes
—	TX	3.3V logic	Control-board serial transmit → adapter RX
—	RX	3.3V logic	Control-board serial receive ← adapter TX
—	GND	0V	Common ground (connect first)
—	VCC	3.3V	Logic reference — usually leave unconnected when the board is self-powered

Serial console at 115200 8N1. The Bible documents the signal set and baud but not a fixed physical pin order — header position is board-specific, so identify TX/RX/GND with a multimeter or scope before connecting (3.3V logic; do not feed 5V TTL).

Source: ANTMINER_ARCHITECTURE.md + HASHBOARD_DIAGNOSTICS.md §11.6 (DIY Fixture / serial console 115200 8N1) · last verified 2026-06

Grounded in the D-Central Mining Bible (PSU_PROTOCOL_BIBLE, HASHBOARD_DIAGNOSTICS, ANTMINER_ARCHITECTURE) — a standard connector/pin reference, no security or exploit detail. Pairs with the ASIC PSU reference, the repair-parts database, the PSU repair guide and the ASIC dimensions & weight reference. Verify pin 1 keying against your specific board before wiring.

Related products, repair, and setup paths

Last reviewed June 22, 2026.