ASIC Control Board Reference
Quick answer
This reference covers 12 ASIC miner CONTROL boards — the controller (SoC) board that boots the firmware and drives the hashboards, distinct from the hashboards that hold the mining chips. For each it lists the SoC, CPU, the models that use it, the hashboard chip family it drives, whether it uses a PIC microcontroller (3 are PIC-less S21-generation boards), and the host interface.
Match the board markings (SoC + NAND + connector) to the right controller before flashing or swapping — control-board revisions vary within a model line. Free CSV/JSON under CC BY 4.0; confirm the exact board revision before servicing.
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| Control Board | SoC | CPU | Models | Hashboard Chips | PIC | Interface |
|---|---|---|---|---|---|---|
| Xilinx Zynq controller (S9-gen; zynq7007 BMU prefix; am1-s9) Boots FSBL + FPGA bitstream + U-Boot from 256MB NAND (or SD via J3 jumper); the root ramdisk is only SHA256-verified, so a DCENT_OS image can replace it while reusing the stock boot chain, building on community open tooling. | Xilinx Zynq-7010 (XC7Z010; XC7Z007S variant) with Artix-7 FPGA fabric | Dual ARM Cortex-A9 @ 667 MHz (Zynq-7010) | S9 / S9i / S9j / T9+ / S9D / R4 | BM1387 (SHA-256) | PIC (PIC16F1704, x3 at I2C 0x55/0x56/0x57) | FPGA UART FIFOs (AXI 0x43C00000) + FPGA AXI-IIC (0x41600000) -> ASIC chain |
| Xilinx Zynq controller (S17/T17-gen; am2-s17) Same Zynq boot chain as the S9 generation but with a 4.6.x kernel; aftermarket OS images typically replace only the NAND ramdisk and reuse the stock FSBL/FPGA, which eases a DCENT_OS port. | Xilinx Zynq-7000 class (XC7Z010 / XC7Z007S) with FPGA fabric | Dual ARM Cortex-A9 @ 667 MHz (Zynq-7010 class) | S17 / S17+ / T17 / T17+ | BM1397 (SHA-256) | PIC (dsPIC33EP16GS202) | FPGA UART FIFOs (AXI) -> ASIC chain |
| Xilinx Zynq controller (S19/T19-gen; C55/C71; am2) C55/C71 boards boot Zynq FSBL + FPGA + U-Boot from NAND with an external SD-recovery slot; DCENT_OS targets them via the same SHA256-only ramdisk-replacement path used on the S9-gen board. | Xilinx Zynq-7010 (XC7Z007S/010) with Artix-7 FPGA fabric | Dual ARM Cortex-A9 @ 667 MHz (Zynq-7010) | S19 / S19 Pro / S19a / S19a Pro (early Zynq C55/C71 boards) | BM1398 (SHA-256) | PIC (dsPIC33EP16GS202) | FPGA UART FIFOs (AXI) + FPGA I2C -> ASIC chain |
| Xilinx Zynq controller (L7 Scrypt; xil-L7) Scrypt-class Zynq controller whose init only sets PSU-enable (gpio907) and LEDs, with the hashboard chain brought up over FPGA UART; a DCENT_OS Scrypt path would mirror the SHA-256 UART driver model. | Xilinx Zynq-7000 class (XC7Z010 family; exact part uncertain) with FPGA fabric | Dual ARM Cortex-A9 (Zynq-7000 class; clock not separately stated) | L7 / L7 Hydro (Scrypt) | BM1489 (Scrypt) | uncertain (PSU enable on GPIO907; voltage-controller type not identified) | FPGA UART FIFOs (AXI) -> ASIC chain |
| BeagleBone-style AM335x controller (BBCtrl / BB18) No FPGA and no kernel modules - ASIC chains are driven over standard Linux UARTs, making this the simplest DCENT_OS target; boots MLO -> U-Boot -> kernel -> ramdisk from NAND or an internal SD card. | TI AM335x Sitara (AM3352 in the board table) | Single ARM Cortex-A8 (clock not stated in Bible) | L3+ / L3++ (Scrypt); late-2021 S19j / S19j Pro stock-BB (BB18 board) | BM1485 (L3+, Scrypt); BM1398 / BM1362 (S19j-era stock-BB) | PIC present (L3+ PIC mac-pairing; dsPIC33EP on S19j-era stock-BB) | Software UART (/dev/ttyO1,2,4) + Linux I2C; no FPGA |
| Cvitek CV1835 controller (CVCtrl / C88, CB8, CB4) Boots an ATF FIP chain (FSBL + OpenSBI + U-Boot) from SPI-NAND with secure boot; third-party OS images commonly run as a reboot-non-persistent overlay, so a clean DCENT_OS install needs network re-injection or a board with the external SD slot. | Cvitek/SOPHGO CV1835 (CV183x family) | Dual ARM Cortex-A53 @ 1.0 GHz (ARMv8-A; runs AArch32 under stock firmware) | S19k Pro / S19 XP / S19j Pro / S19j XP / S21 / T21 / KS3 / KS5 / X5 / L9 (C88/CB8/CB4 boards) | BM1362 / BM1366 / BM1368 (S21) / BM1489 (L9) | PIC (dsPIC33EP) | UART (stock uart_trans.ko or userspace software UART) + Linux I2C; no FPGA |
| Amlogic AXG controller (AMLCtrl / am3-aml; C76, C81, C83, CBE) Quad-A53 AXG with secure boot from SPI-NAND and micro-USB OTG recovery (firmware-blocked on units shipped Sept 2025+); S21-gen boards drop the PIC, consistent with the chip canon, and share a common power-on init across the S21 family. | Amlogic A113D (AXG SoC family) | Quad-core ARM Cortex-A53 @ 1.2 GHz (ARMv8-A; ARM64 kernel, armhf userspace) | S19j Pro / S19 XP / S19k Pro / S21 / S21 Pro / S21 XP / S21+ / L9 (C76/C81/C83/CBE boards) | BM1362 / BM1366 / BM1368 / BM1370 / BM1489 (L9) | PIC (dsPIC33EP) on S19j-era boards; No-PIC on S21 generation (TAS5782M DAC drives VID) | Software UART (/dev/ttyS1-4) + Linux I2C; no FPGA |
| ESP32-S3 self-contained controller (BitAxe-class open hardware) Self-contained open-hardware controller driving one ASIC over UART+I2C with a TPS546 buck regulator; firmware is flashed directly over USB, making it the most accessible DCENT-class target and the spirit of building on prior open work. | Espressif ESP32-S3 | Espressif ESP32-S3 microcontroller | BitAxe Ultra / Hex Supra (BM1366), BitSupra (BM1368), BitAxe Gamma (BM1370), BitAxe Touch (BM1370, planned) and similar open single-board miners | BM1366 / BM1368 / BM1370 (single-chip) | No-PIC (TPS546 buck regulator; single ASIC) | UART + I2C direct to a single ASIC |
| Allwinner H-series controller (WhatsMiner / MicroBT; H3, H6, H616) OpenWrt/procd controller where cgminer selects a per-model UCI profile from the EEPROM chip_id and drives the chain over a UART command-byte protocol. | Allwinner H3 / H6 / H616 | Allwinner H3 / H6 / H616 (cores not detailed in Bible) | WhatsMiner M1-M3 / M8-M12 / M19-M20S / M50-M60S / D-series (MicroBT) | MicroBT K-series (K1/K2/K3/D) - not Bitmain BM | No-PIC (UART command-byte voltage control) | UART command-byte protocol (per-model profile from EEPROM chip_id via UCI) |
| Innosilicon ARMv7 controller (T-series) Custom ARMv7 SoC running a cgminer fork with an mcompat hardware-abstraction layer for voltage/PWM. | Custom Innosilicon ARMv7 SoC | Custom Innosilicon ARMv7 SoC (cores not detailed in Bible) | Innosilicon T2Tz (DragonMint-T1 heritage T-series) | Innosilicon T2T - not Bitmain BM | uncertain (mcompat HAL PWM voltage backend; not PIC-based) | uncertain (mcompat HAL, PWM_SOC_HUB backend) |
| Kendryte K210 controller (Avalon industrial; bare-metal) Bare-metal RISC-V controller with no Linux init; the mm_miner image is AES-CBC encrypted with the key in K210 OTP eFuse, so the platform is effectively closed to custom firmware. | Kendryte K210 (RISC-V) | Kendryte K210 (RISC-V; bare-metal, no Linux init) | Avalon A1346 / A14x / A15x (Canaan industrial) | Canaan Avalon A3197S / A3198S / A3200C-Plus - not Bitmain BM | uncertain (voltage control encrypted in mm_miner firmware) | uncertain (encrypted mm_miner; K210 SPI-flash bootloader -> main loop) |
| Kendryte K230 Linux controller (Avalon home-class) Newer RISC-V controller that runs Linux on Canaan's home-class miners (incl. the Avalon Mini 3); board and chip details still flagged TBD in the Bible. | Kendryte K230 (RISC-V) | Kendryte K230 (RISC-V; runs Linux) | Avalon Nano 3 / 3S / Mini 3 (Canaan home-class; some fields uncertain) | Canaan Avalon home-class chips (uncertain) - not Bitmain BM | uncertain | uncertain |
Source: the D-Central Mining Bible (ANTMINER_ARCHITECTURE + MASTER_CHIP_CATALOG) + the Laval ASIC repair bench. Pairs with the ASIC chip reference, the PSU reference and the miner spec database.
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Last reviewed June 20, 2026.