Hashboard Test Fixture & ASIC Chip Tester: How Bench Testing Works

What a hash-board test fixture actually is

An Antminer is four boards working together: one control board running Linux and the mining client, three hash boards, a power supply and the fans. When a hash board is suspect, you do not want to keep swapping it in and out of a live miner to test it. A test fixture replaces the whole miner with a single bench rig whose only job is to talk to one hash board. At its core sits an FPGA (or a salvaged control board of the same generation) that emulates the control board’s hash-board interface: it drives the reset line, clocks the chain, speaks the chips’ UART protocol, reads the on-board temperature sensors and EEPROM over I²C, and measures current and voltage. Around that sit a current-limited 12–15V supply (up to ~50A for a full hash test), mandatory cooling fans, status display, and discharge resistors to bleed the rails safely afterwards. Connection to the board is the same 18-pin signal cable and power terminals the miner itself uses.

The point is isolation. On the bench you can power one board, watch exactly which chips respond, probe a single signal at a domain boundary and read each domain’s voltage — none of which is practical inside an assembled, running machine.

How per-domain and per-chip testing works

Every BM-series ASIC on a hash board is wired two ways at once. For power, chips are grouped into voltage domains — small clusters that share one regulated rail, stacked in series so the board’s input voltage is divided across them (an S19 has 76 chips in 38 domains at ~0.36V each; an S21 has 108 chips in 12 domains at ~1.2V each). For data, all the chips form a single UART daisy chain: commands flow forward from chip to chip, responses flow back the other way. A test fixture exploits both structures. It measures each domain to find power faults, and it enumerates the chain to find signal/communication faults — because those are two different failure families that need two different reads.

Background on the silicon and boards this rests on: the ASIC chip reference (chip → model → board → domain map) and the control-board reference (which SoC drives which generation).

The three diagnostic signals a fixture reads

1. Voltage-domain continuity and voltage

Unpowered, a multimeter in resistance mode across each domain test point should read consistently from domain to domain; a domain that reads far lower is shorted (a failed chip or blown capacitor), far higher is open (a cracked joint or broken trace). Powered on the fixture, each domain’s voltage should sit within about ±50mV of its neighbours — a domain more than ~100mV low points at a partial short, well above average points at an open. An abnormal voltage between domains will stop the whole board, which is why the domain sweep is the first powered read. The exact factory pass/fail figures live in the ASIC diode & voltage reference — and note the important nuance documented there: the factory “diode” figures are resistance in ohms, not a forward-voltage drop.

2. BM-series chip detection (enumeration)

This is the headline test. The fixture asserts reset, deactivates the chain, then assigns sequential addresses down the line and counts how many chips reply over UART. The detected count is compared to the model’s expected count; a shortfall is reported as the number of missing chips. Crucially, because the chain is serial, a single dead chip makes every chip after it invisible — so a board reporting, say, 29 of 108 chips has its break at the 30th position, not 79 separate failures. Repairers narrow the exact chip with a binary-search (dichotomy) method, injecting a known-good response at the chain midpoint and watching whether the count climbs. A shorted chip behaves differently: it can pull signal lines down and make the whole chain read as zero.

3. The diode / resistance method (component level)

Before or instead of powering a board, a multimeter in diode/resistance mode checks individual chip pins and rails against reference values: the bus signals (BI/BO), reset (RST), the UART lines (RX/RI, TX/CO), the clock (CLK) and the per-domain LDO outputs (1.8V and 0.8V). A reading far from the known-good figure localises the fault to a pin, a regulator or a passive. The one rule that protects the board: the black probe goes to a real ground point, never to the heatsink, which can short a live domain. Full per-pin figures by model are in the diode & voltage reference; the connectors you probe through are mapped in the connector pinout reference.

What a single-chip (ASIC) tester reveals

A standalone chip tester is a fixture scaled down to a single ASIC socket. Its job is narrow but valuable: prove that one BM-series chip — a freshly bought replacement, or a chip salvaged and re-balled from a donor board — can initialise (accept an address, respond over UART, report a sane temperature and core voltage) and ideally pass a pattern test, before it is reflowed onto a $1,000+ hash board. Without that step, a repairer can spend an hour soldering a chip that was dead on arrival, then chase a phantom board fault. Chip-level testers exist for the modern Bitmain families — the BM1366 (S19 XP / S19K Pro class), BM1368 (S21 / T21) and BM1370 (S21 Pro / S21 XP) — because hand-soldering a counterfeit or DOA chip is one of the most expensive mistakes in board repair. It is the bench equivalent of testing a fuse before you wire it in.

The bench method, step by step

Production and repair testing follows a deliberate, ordered sequence — the same logic whether the rig is a commercial fixture or a do-it-yourself one. The three powered stages are universally referred to as PT1 (enumeration), PT2 (pattern) and PT3 (frequency sweep), and a repaired board is always re-run from the top:

1. Inspect the board cold, before any power. On an ESD-safe mat, examine the board under magnification: burnt or shifted components, cracked solder on the domain-boundary resistors, a cracked 25 MHz crystal, connector damage and any foreign solder balls bridging a short. Most faults are visible before a single volt is applied.
2. Run the unpowered resistance / diode-mode checks. With power disconnected and capacitors discharged, set a bench multimeter to resistance (diode) mode. Black probe on board ground — never the heatsink, which can short the board. Read each voltage-domain test point and each chip signal pin (BI/BO, RST, RX/RI, TX/CO, CLK, the 1.8V and 0.8V LDOs) and compare against a known-good board or the factory reference figures. A near-zero domain reading is a short; a much higher reading is an open.
3. Mount the board on the test fixture. Connect the hash board to the fixture through the 18-pin signal cable (inserted last) and the high-current power input. The fixture stands in for the miner control board: an FPGA or a salvaged control board drives the chain over UART, a current-limited 12–15V supply feeds the board, four fans run at full speed and discharge resistors are wired for after the test.
4. PT1 — enumerate the chips. Power on and let the fixture assert reset, send CHAIN_INACTIVE, then walk SET_CHIP_ADDR down the daisy chain at 115200 8N1. Each chip that answers is counted. Compare the detected count to the model’s expected count (for example 108 on an S21). If the fixture reports fewer chips than expected, the chain breaks at the chip immediately after the last one detected.
5. PT2 — pattern-test each chip. Send known SHA-256 test vectors to every chip and compare each returned nonce against the expected result. A chip that returns a wrong nonce, an incomplete response or nothing is flagged by address — this separates a chip that merely enumerates from one that actually hashes correctly.
6. PT3 — sweep the frequency under cooling. With the heatsink properly mounted on fresh thermal interface and a fan attached, ramp the clock from a low frequency toward the model’s rated frequency, verifying hash output at each step. A chip that reads zero once frequency climbs, or a domain that overheats, fails here. A repaired board is always re-tested from PT1.
7. Discharge and record. Power down, let the discharge resistors bleed the rails, and log the result: chip count, any failing addresses, the domain-voltage spread and the frequency at which a fault appeared. That record is what turns a vague “board is dead” into a specific, repairable fault.

Building a fixture without a factory rig

A working fixture does not require proprietary hardware. A budget-conscious shop can reproduce the function with a salvaged control board of the matching generation, a USB-to-TTL adapter on its serial console (115200 8N1), a bench supply capable of the board’s full-load current, four fans for cooling and the correct test configuration on an SD card. The control board already knows how to enumerate and drive its own hash boards; the adapter simply lets a PC watch the diagnostic output. We describe the method here and deliberately host none of the vendor test firmware, encrypted fixture binaries or factory board files that some kits ship — those are copyrighted, and you do not need a copy of them to understand how a fixture works. If you want the underlying signal map to build against, it is all in the open references linked throughout this page.

Standing on the shoulders of giants

None of this is D-Central’s invention. The reason open hash-board testing is possible at all is that the wider mining and repair community — independent repair benches who published their test-point maps, and the open-source firmware authors who reverse-engineered the BM-series UART protocol (the skot9000 / Open Source Miners United and ESP-Miner work behind the Bitaxe, which drives a single BM chip with fully open firmware) — did the hard work in public first. Bitmain and the other manufacturers designed the silicon and the production test flow. We have simply gathered the verified method into one plain-English reference, grounded in our own Laval repair bench and the D-Central Mining Bible, so the next person does not have to start from zero.

Keep going: the diode & voltage reference (factory pass/fail figures) · the connector & pinout reference · the repair-tools & bench-kit list · the replaceable-parts database · the deeper chip-level hashboard repair deep-dive and guide to hashboard testers. Not a DIY job? The fault finder and our ASIC repair service can take it from here. Grounded in the D-Central Mining Bible (HASHBOARD_DIAGNOSTICS, ANTMINER_ARCHITECTURE, DIODE_VOLTAGE_REFERENCE) and the Laval bench — method only, no security or exploit detail, no hosted vendor fixture files.