EUV Lithography

EUV (extreme ultraviolet) lithography is the chip-patterning technique that uses light with a wavelength of just 13.5 nanometers to print the finest circuit features on a silicon wafer. Because that wavelength is roughly fourteen times shorter than the 193nm deep-ultraviolet light it supplements, EUV can resolve patterns far smaller in a single exposure, enabling the 7nm, 5nm, 3nm, and 2nm-class processes used for cutting-edge logic — including the most advanced Bitcoin mining ASICs, whose chip generations track the foundry roadmap: the 7nm era that produced chips like the BM1397, the 5nm era of the BM1362, and successive nodes since. Every step down that ladder is, in large part, an EUV story.

How the light is made

EUV light cannot be produced by any convenient laser, so it is generated by brute force. Inside the scanner, around 50,000 droplets of molten tin per second are fired into a vacuum chamber and struck by two pulses from a high-power CO2 laser: a pre-pulse flattens each droplet into a pancake, and the main pulse vaporizes it into a plasma hot enough to radiate at 13.5nm. Because air and every known lens material absorb EUV, the entire optical path runs in vacuum and uses precision Bragg-mirror optics — multilayer molybdenum-silicon stacks flat to atomic tolerances — rather than lenses; even the photomask is reflective rather than transmissive. Each mirror absorbs a share of the light, so the source must be ferociously bright for enough photons to survive the journey to the wafer. It is plausibly the most complex manufacturing tool ever built, and ASML of the Netherlands is the only company in the world that makes it, supplying TSMC, Samsung, and Intel.

Why it matters for mining silicon

Before EUV, printing features beyond 193nm immersion's native resolution required multi-patterning: decomposing one layer into several aligned exposure-and-etch passes, each adding cost, time, and yield-killing overlay error. A single EUV exposure replaces several such passes at the most critical layers, improving yield and economics at the leading edge — the same leading edge that drives down joules per terahash, the number that decides which mining hardware survives a halving. The follow-on generation, high-NA EUV, extends resolution further with wider-aperture optics for the nodes now arriving.

The centralization question

For a community that cares about decentralization, EUV is a sobering data point: the entire leading edge of computing — mining chips, AI accelerators, phone SoCs — flows through one toolmaker's machines installed in a handful of foundries, making it one of the most concentrated chokepoints in any modern supply chain and an object of active export-control politics. Miners feel this directly in ASIC pricing, generational cadence, and geographic concentration of manufacturers. The honest takeaway is not that the chokepoint can be wished away, but that resilience lives downstream: open firmware, repairable hashboards, and hardware kept productive long past its warranty loosen dependence on the next node. EUV is what makes today's FinFET and GAAFET transistor structures manufacturable at scale; see tape-out for the design-side milestone that commits a chip to these machines.

The economics deserve one more number: EUV scanners cost well north of a hundred million dollars apiece, require a fleet of cargo aircraft to deliver, and are produced at a rate of only a few dozen per year, so fab construction schedules are planned around their delivery slots. When ASIC vendors talk about wafer allocation, this is the machinery behind the sentence — leading-edge capacity is rationed years in advance, and a mining chip competes for the same EUV exposures as flagship phone and AI silicon. Efficiency-per-watt roadmaps in mining are, at bottom, delivery schedules for tin-plasma light sources.