Multi-Patterning

Multi-patterning is a family of fabrication techniques that print a single chip layer using more than one exposure or deposition step, so that the final feature pitch is tighter than any one lithography exposure could resolve. It became essential below the 20nm node, where the wavelength of available light could no longer directly image the required density, and it remains important even alongside EUV for the very densest layers.

Pitch-splitting and spacers

The simplest form, litho-etch-litho-etch (LELE) or double patterning, decomposes a dense target pattern into two sparser patterns, prints each in turn, and interleaves them to double the line density. A more elegant variant, self-aligned double patterning (SADP), prints lines at double pitch, deposits a thin film over them, then etches it so only the sidewall "spacers" remain; removing the original lines leaves twice as many features, self-aligned without a second mask. Repeating the idea yields quadruple patterning and beyond.

Cost, error, and the EUV trade-off

Every extra exposure adds masks, process steps, alignment risk, and cost, and overlay errors between passes can hurt yield. That economic pressure is a major reason the industry adopted 13.5nm EUV light, which collapses several multi-patterning passes back into a single exposure for many layers, although multi-patterning still backs up EUV at the tightest pitches used in advanced mining ASICs.

Multi-patterning works hand in hand with EUV lithography to reach the densities behind modern transistor density figures.