Latch-Up

Latch-up is a destructive failure mode unique to CMOS in which an unintended low-impedance path forms directly between the power and ground rails inside a chip. Every CMOS layout contains hidden parasitic bipolar transistors — a PNP and an NPN formed by the doping wells and junctions that make up the normal NMOS and PMOS devices. Together they create a four-layer PNPN structure that is electrically identical to a thyristor, or silicon-controlled rectifier (SCR). Under the right trigger this parasitic SCR turns on, and once on, it holds itself on: the chip is latched into conducting a short between its own supply rails until power is removed or the silicon burns.

How the trap springs

The mechanism is regenerative feedback. If one parasitic transistor starts conducting — because a transient injected current into a well — its collector current becomes base current for the other transistor, which conducts and feeds current right back to the first. The loop gain exceeds one, both devices saturate, and the path latches. Current then floods from supply to ground limited only by what the rail can deliver, and a modern power rail can deliver a lot. Junction temperatures climb within milliseconds; bond wires fuse, metallization melts, and the device suffers permanent damage. Classic triggers include voltage overshoot on an I/O pin beyond the supply rail, supply transients during hot-plugging, an ESD strike that injects charge into the substrate, and even ionizing radiation in extreme environments. Critically, the trigger can be brief and survivable on its own — it is the self-sustaining latch that kills.

How designers prevent it

Chip designers fight latch-up by breaking the feedback loop below the gain needed to sustain it: guard rings and isolation trenches around sensitive transistors, generous well and substrate taps that lower the parasitic resistances, physical spacing between NMOS and PMOS regions, and epitaxial or silicon-on-insulator processes that starve the parasitic devices outright. Some power-management parts add active latch-up detection that crowbars the supply when abnormal current appears. Robust board design helps too — clamping diodes, controlled power sequencing, and solid ESD protection keep triggers from reaching the die in the first place.

What it looks like on the repair bench

For an ASIC repair technician, latch-up is one explanation for the board that suddenly draws enormous current and gets hot at one spot for no visible reason. A hashboard that was hashing normally, took a power glitch or a static zap during handling, and now presents a hard low-resistance short on a domain rail may have a latched chip rather than a mechanically failed one. The diagnostic tell: if cutting power and re-applying it clears the short, the SCR had latched but the silicon survived; if the short persists cold, the latch-up event has already cooked the die and the chip needs replacement. This is one reason disciplined handling matters — wrist straps, grounded mats, and never hot-plugging hashboards onto a live PSU. Power sequencing exists precisely so that I/O never leads the supply rail.

Latch-up also explains a design detail visible all over mining hardware: the conservative sequencing between the control board's 3.3V logic rails and the high-current domain supplies. Bring-up order is not cosmetic — applying signals to an unpowered chip forward-biases exactly the junctions that trigger the parasitic SCR. When a repair guide insists on connecting the ribbon cable before applying PSU power, this failure mode is a large part of the reason.

Latch-up is CMOS biting itself: a parasitic device the designer never wanted, sitting dormant in every chip, waiting for a transient. Prevention through clean power and careful handling is the real defense, because by the time you can measure the fault, the margin for saving the part is thin. If a board in your fleet shows sudden overcurrent behavior you cannot trace, that is exactly the class of fault a professional bench diagnosis at D-Central's repair service is built to isolate before it takes the rest of the board with it.