PCI Express (PCIe)

PCI Express (PCIe) is the high-speed expansion bus that modern computers use to connect add-in cards such as graphics cards, network adapters, and NVMe storage to the host system. It replaced the older parallel PCI and AGP buses with point-to-point serial links, which removed the shared-bus bottleneck — every device gets its own dedicated connection to the host rather than fighting for time on a common set of wires — and let bandwidth scale cleanly with each new generation.

Lanes and generations

PCIe organises bandwidth into lanes. A single lane is one differential transmit pair plus one receive pair; slots are built as x1, x4, x8, or x16, the number indicating how many lanes are wired. More lanes mean proportionally more bandwidth, and successive generations roughly double per-lane throughput: PCIe 3.0 delivers about 985 MB/s per lane, PCIe 4.0 about 1.97 GB/s, and PCIe 5.0 about 3.94 GB/s. A device and slot negotiate the highest common generation and lane width at link-up, and they also negotiate down gracefully — a x16 card in a x4 slot, or a Gen4 drive on a Gen3 board, simply runs at the lesser rate. That negotiation is worth remembering on the bench: a card seated slightly askew or a damaged slot will often train at x1 and "work" while quietly delivering a fraction of its bandwidth.

Why it matters for mining rigs

GPU mining rigs lean on PCIe in an unusual way. A graphics card hashing on a memory-bound algorithm sends almost no data across the bus once a job is loaded — work units are tiny and results tinier — so the link can be throttled to a single lane without hurting hashrate. This is why miners run powered x1-to-x16 risers: a x1 connection feeds the card data while a separate cable delivers power, letting one motherboard host six or more GPUs spread out for airflow. ASIC miners, by contrast, do not use PCIe internally at all: an Antminer's control board talks to its hashboards over simple serial links through a ribbon cable, because moving mining work needs kilobits, not gigabytes. PCIe earns its complexity only where real data volume flows.

Why it matters for local AI

Self-hosted inference flips the mining calculus. Loading a multi-gigabyte model into a GPU's VRAM crosses the PCIe bus, so link width determines how long a model swap takes; and any setup that spills model layers to system RAM, or splits a model across multiple GPUs, pushes traffic over PCIe continuously — where a starved x1 riser that was fine for mining becomes a genuine bottleneck. A repurposed mining frame can absolutely serve as a local AI rig, but the risers usually have to go: inference wants the widest link the board can give each card. Once a model fits entirely in VRAM, though, token generation touches the bus only lightly, which is why modest hosts drive big GPUs perfectly well for single-model serving.

Power is the other half of the slot

A PCIe x16 slot delivers up to 75 W to the card; anything hungrier draws the balance through auxiliary connectors from the PSU. Mining history offers a cautionary tale here: cheap risers powered by SATA connectors — rated well below what a GPU can pull through a riser — were a notorious fire hazard in the GPU-rig era, and the survivors' rule stands for any repurposed rig: feed risers and cards from proper PCIe power connectors, distribute load across the supply's cables, and treat any melted connector as a design error, not bad luck. The data lanes are delicate too — PCIe's high-speed differential pairs are unforgiving of oxidized contacts, so reseating a card that trains at reduced width is a legitimate first repair step.

For the physical slot that PCIe cards plug into, see edge connector; for the broader idea of how components share a data path, see system bus.