Phase-Locked Loop (PLL)

A phase-locked loop (PLL) is a feedback control circuit that produces an output clock whose phase and frequency are locked to a reference clock. In a mining ASIC the board supplies a relatively slow, stable crystal reference (often tens of MHz), and the on-chip PLL multiplies it up to the hundreds-of-MHz or low-GHz frequency at which the hash engines actually run. Every clock you set from firmware is, underneath, a PLL multiplier setting.

How it locks

A PLL compares the phase of a divided-down copy of its own output against the reference using a phase detector. The resulting error drives a charge pump and loop filter, which tunes a voltage-controlled oscillator until the two are aligned. With a feedback divider of N, the output settles at N times the reference (an integer-N PLL), so the chip can synthesize a precise high frequency from a cheap, accurate crystal.

Why it matters for miners

Overclocking and undervolting both lean on the PLL: raising the multiplier raises engine frequency and hashrate but also raises power and heat, while the silicon can only follow the faster clock if the supply voltage is high enough. PLLs also need a clean, low-jitter supply; noisy power or marginal grounding can cause the loop to lose lock, which shows up as hashboard instability or chips dropping out. The PLL output then fans out through the chip's clock tree.

The frequency it produces feeds the clock tree, and the voltage that lets engines follow that clock is governed by the voltage domain.