Clock Tree

A clock tree is the network of wires and buffers that distributes a single clock signal from its source to the thousands or millions of sequential elements (flip-flops) spread across an ASIC die. The goal is that every element sees the rising edge at almost the same instant. In a mining chip the clock tree carries the PLL output across the full array of hash engines.

Skew and clock tree synthesis

The difference in arrival time of the clock at two different flip-flops is called skew. Too much skew breaks the timing relationship between launching and capturing registers, corrupting computation. Designers use clock tree synthesis (CTS) tools to insert and size buffers along every branch so path delays match. Classic balanced topologies such as the H-tree route the clock symmetrically so distant corners of the die are reached with equal delay.

Relevance to mining hardware

The clock tree is one of the most power-hungry nets on the chip because it toggles every cycle and drives an enormous fan-out. That continuous switching is a meaningful slice of an ASIC's dynamic power, which is why power-saving tricks like gating the clock target it directly. When a chip is pushed to high frequency, the clock tree is also where timing margin runs out first, contributing to the instability seen when overclocking too aggressively.

The clock that flows through the tree is generated by the phase-locked loop, and switching it off in idle blocks is the job of clock gating.