Phase-Locked Loop (PLL)

A phase-locked loop (PLL) is a feedback control circuit that produces an output clock whose phase and frequency are locked to a reference clock. In a mining ASIC the board supplies a relatively slow, stable crystal reference (typically tens of MHz), and the on-chip PLL multiplies it up to the hundreds-of-MHz frequency at which the hash engines actually run. Every clock you set from firmware is, underneath, a PLL configuration: the mining software calculates divider and multiplier values for the target frequency, writes them to the chip's PLL registers over the serial chain, and waits for the loop to report lock before hashing resumes.

How it locks

A PLL compares the phase of a divided-down copy of its own output against the reference using a phase detector. The resulting error signal drives a charge pump and loop filter, which tunes a voltage-controlled oscillator until the two inputs are aligned — at which point the loop is "locked" and the output tracks the reference with a fixed multiplication ratio. With a feedback divider of N, the output settles at N times the reference (an integer-N PLL); fractional-N designs allow finer steps. The elegance is that frequency precision comes almost free: a cheap quartz crystal is extremely stable, and the PLL transfers that stability up to frequencies the crystal itself could never oscillate at. The same principle runs the control board too — the Zynq SoC on many Antminer control boards derives its 667MHz ARM core clock from PLLs multiplying a modest board oscillator.

Frequency scaling in practice

Overclocking and underclocking both lean on the PLL: raising the multiplier raises engine frequency and hashrate but also raises power and heat, while the silicon can only follow the faster clock if the supply voltage is high enough for its transistors to switch in time. That coupling between frequency and voltage is the entire game of efficiency tuning, and it is why autotuning firmware treats them as a pair — measuring each hash domain's real behavior and calculating per-chain frequency settings at runtime rather than applying one fixed profile. Voltage, note, is adjusted per domain on the board's regulation hardware; the PLL is what gives frequency its per-chip granularity.

When the loop misbehaves

PLLs need a clean, low-jitter supply and a healthy reference to hold lock. On the repair bench, PLL trouble shows up as boards that enumerate their chips but hash erratically, chips that drop out under load, or frequency settings that mysteriously won't apply. Common physical culprits: a cracked or contaminated crystal (check the reference with a scope), degraded decoupling on the PLL's supply pin, or marginal power rails sagging under load — the loop loses lock exactly when current demand peaks. Because the lock-wait is part of the frequency-setting sequence, a chip whose PLL never locks can also stall initialization for its whole chain segment. If a board fails only at higher frequency settings but is stable at stock, suspect voltage margin before suspecting the PLL itself.

The frequency the PLL produces fans out through the chip's clock tree, and the supply that lets the engines follow that clock is governed by the voltage domain.

One more property worth knowing: PLLs take real time to settle. Lock is reached in microseconds to milliseconds depending on loop bandwidth, which is why frequency changes on a miner are sequenced — write registers, wait for lock, resume hashing — rather than instantaneous, and why tuning firmware steps frequency gradually instead of jumping. If you script frequency changes yourself, respect the settle time; commanding a new value before the previous lock completes is a classic way to produce the mysterious instability you were tuning to avoid.