Definition
Clock gating is a low-power design technique that disables the clock signal to a circuit block whenever that block has no useful work to do. Because dynamic power is burned every time a flip-flop or net toggles, stopping the clock to an idle region stops nearly all of its switching activity, and therefore its dynamic power, while leaving its stored state intact.
How it works
A small gating cell sits between the clock tree and a group of registers. When an enable signal says the block is inactive, the cell holds the local clock steady so the downstream logic freezes instead of toggling pointlessly. When work resumes, the clock is re-enabled. Modern synthesis tools insert clock gating automatically across millions of registers, and it is one of the most effective dynamic-power reductions available because the clock network itself is such a heavy switcher.
Relevance to mining ASICs
Mining chips are designed to run their hash engines flat out, so clock gating shows up less in the hot core than in control, configuration, and interface logic that only works intermittently. It also matters during partial operation, for example when a firmware throttles or disables part of the array; gated regions stop drawing dynamic power even though they remain powered. Note the distinction from cutting power entirely: clock gating still leaks static current because the transistors stay energized.
Clock gating only stops the clock; to also kill the static leakage of an idle block you need power gating, and the clock it gates is delivered by the clock tree.
In Simple Terms
Clock gating is a low-power design technique that disables the clock signal to a circuit block whenever that block has no useful work to do.…