Power Gating

Power gating is a low-power technique that completely cuts the supply voltage to a region of a chip when it is idle. Unlike clock gating, which only stops switching activity, power gating removes power from the block altogether, so it eliminates not just dynamic power but also static leakage current, which would otherwise keep flowing as long as the transistors are energized.

How it works

A power-gating design inserts large 'sleep' transistors (header or footer switches) between the always-on power rails and the block's local power net. When a control signal puts the block to sleep, the switches open and the region's supply collapses toward zero. Because the block loses power, its internal state is lost unless it is saved first, and waking it up costs time and energy as the local net recharges. That overhead is the price of killing leakage.

Relevance to mining hardware

In leading-edge process nodes, leakage can be a large fraction of total power, so power gating is the only way to truly shut off an unused block rather than merely quieting it. In a mining ASIC this is most relevant to peripheral or redundant logic and to coarse power management, since the hash engines are meant to run continuously. The trade-off, wake-up latency and the need to preserve or reload state, is why it is reserved for blocks that are idle long enough to repay the cost.

Where power gating removes the supply to stop leakage, clock gating only stops the clock; the static current it targets is leakage current.