Leakage Current

Leakage current is the current that flows through a transistor when it is nominally "off" and not actively switching. It produces static power, dissipated continuously just because the chip is powered, independent of how much work the logic is doing. As process geometries have shrunk, leakage has grown from a rounding error into a major component of total chip power, and for a mining ASIC that lives or dies on joules per terahash, it is one of the physical realities that tuning must respect.

Where it comes from

The dominant source in modern CMOS is subthreshold leakage: current that trickles between source and drain because scaled transistors have lower threshold voltages and can never fully turn off. A second source is gate leakage, where charge tunnels quantum-mechanically through the ultra-thin gate oxide of advanced nodes. Junction leakage through the source and drain diodes adds a smaller share. All of these worsen as geometries shrink, and subthreshold leakage in particular rises steeply with temperature, roughly exponentially, which sets up the feedback loop that matters most in practice.

The thermal feedback loop

A hot chip leaks more; the extra leakage is dissipated as heat; the chip gets hotter still. On a densely packed hashboard, this loop is why cooling quality shows up directly in efficiency numbers, not just in reliability. Keeping junction temperatures down reduces static power, which improves J/TH at the same clock and voltage. It is also why immersion-cooled or well-ducted machines can run tighter operating points than the same silicon gasping in a hot closet, and why a fouled heatsink quietly costs money every hour before it ever causes an error.

How designers fight it

Chip designers attack leakage with a standard toolkit. Multi-threshold libraries place slow, high-threshold transistors everywhere speed is not critical, reserving leaky fast transistors for critical paths. Power gating cuts the supply to idle blocks entirely, reducing their static draw to nearly nothing. Body biasing shifts thresholds dynamically, and careful thermal design keeps the exponential temperature term in check. Mining ASICs, built on aggressive nodes and run flat-out around the clock, lean hardest on the last lever: voltage. Because leakage falls off strongly with supply voltage, undervolting attacks static and dynamic power at once.

What it means at the tuning table

This is where leakage meets everyday mining practice. Every chip on a board leaks differently, silicon lottery is real, and leakage is a big part of it, which is why autotuning firmware profiles each voltage domain and calculates per-domain operating points at runtime rather than applying one factory number. Voltage on these machines is controlled per domain, groups of chips sharing a rail, so the tune must find the setting the leakiest chip in each domain can tolerate. Cooler intake air, clean heatsinks, and good airflow give the tuner room to drop voltage further, and the leakage savings compound with the dynamic-power savings. For the home miner, the takeaway is concrete: efficiency is not fixed at the factory. The same hashboard, run cooler and tuned per domain, genuinely consumes fewer watts per terahash, and leakage current is a large part of the physics behind that fact.

Leakage also explains a subtlety in how machines age. As silicon accumulates hours at high temperature, degradation mechanisms shift transistor thresholds, and the leakage profile of a board slowly drifts from its factory characterization. A tune that was stable in a machine's first winter may throw hardware errors two summers later, not because anything broke, but because the silicon's static-power behaviour moved. Re-running the autotune after a deep clean, a repaste, or a season of hot running costs nothing and re-anchors the operating point to the silicon as it is today, rather than as it was on the test stand.