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Dennard Scaling

Hardware

Definition

Dennard scaling is the scaling law, formulated in a 1974 paper led by IBM's Robert Dennard, stating that as transistors shrink their power density stays roughly constant. In its ideal form, when you scale a transistor's dimensions down by some factor, you also scale its voltage and current down by the same factor, so power per unit area holds steady even as you pack in more, faster transistors. For decades this is what let chips, and later mining ASICs, get both denser and more efficient at the same time.

The free lunch it provided

From the mid-1970s to the mid-2000s, Dennard scaling meant each new node delivered more transistors that switched faster without raising the total power budget. This is the deeper reason Moore's Law felt like pure progress: more transistors did not mean a proportionally hotter chip. Mining was an extreme beneficiary, since efficiency gains came almost automatically with each shrink.

The breakdown around 2005

By 2005 to 2006 the law broke down. Supply voltage could no longer fall in step with size, because pushing the threshold voltage lower caused leakage current to rise exponentially, a limit rooted in the 60 mV/decade subthreshold-swing floor of conventional transistors. Power density stopped staying flat, clock speeds stalled, and the industry pivoted to multi-core designs and, later, 3D transistors to keep heat in check, exactly the leakage problem that drives mining-ASIC efficiency engineering today.

The end of Dennard scaling pushed designers toward the FinFET, and it is a separate phenomenon from the still-cited Moore's Law.

In Simple Terms

Dennard scaling is the scaling law, formulated in a 1974 paper led by IBM’s Robert Dennard, stating that as transistors shrink their power density stays…

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