Definition
A clock domain is a region of a chip driven by a single clock. A clock domain crossing (CDC) happens whenever a signal travels from logic clocked by one clock into logic clocked by another that is asynchronous, at a different frequency, or in an unrelated phase. A typical ASIC has several domains, for example a fast hashing domain and a slower control or interface domain, so crossings between them are unavoidable.
The metastability problem
If a signal changes right as the receiving clock samples it, the capturing flip-flop can enter metastability, an unstable state that is neither a clean 1 nor a clean 0 and may resolve unpredictably. Propagated downstream, that ambiguity corrupts data and causes intermittent, hard-to-reproduce failures, exactly the kind of flaky behaviour that is maddening to diagnose in the field.
How it is handled
Designers insert synchronizers at every crossing. The classic two-flip-flop synchronizer samples the incoming signal, then gives any metastability a full clock cycle to decay before a second flip-flop captures a now-settled value. Multi-bit buses use additional structures such as gray-coded counters or asynchronous FIFOs so that no two bits are misaligned across the boundary. Verifying that every crossing is properly synchronized (CDC verification) is a standard, mandatory step in taping out any chip with multiple clocks.
The clocks that define each domain are produced on-chip by the phase-locked loop and delivered by the clock tree.
In Simple Terms
A clock domain is a region of a chip driven by a single clock. A clock domain crossing (CDC) happens whenever a signal travels from…