Process Node

A process node is the name given to a particular generation of semiconductor manufacturing technology, expressed in nanometers: 7 nm, 5 nm, 3 nm. Historically the number tracked a real physical dimension such as transistor gate length, and shrinking it meant every feature on the chip literally got smaller. Since roughly the late 1990s, however, node names have drifted into marketing labels: no feature on a "5 nm" chip is actually five nanometers across. What survives of the original meaning is direction, a smaller-numbered node still broadly indicates denser, faster, more energy-efficient transistors, and in Bitcoin mining that direction is the whole game.

Why the node drives mining efficiency

For mining, the process node is one of the strongest single predictors of a chip's energy efficiency, measured in joules per terahash. A SHA-256 ASIC is almost nothing but hashing cores repeated thousands of times, so shrinking the transistor directly multiplies how many cores fit in a die and divides the energy each hash consumes. The progression is visible across Antminer generations: the 7 nm BM1397 brought the S17 family into the 40-55 J/TH range, the S19-era BM1398 reached about 29.5 J/TH, the BM1362 of the S19j Pro line moved to TSMC's 5 nm class, and the S21-generation BM1368 and BM1370 pushed to roughly 17.5 and 15 J/TH respectively. Each step is the same silicon economics: more hashing logic per square millimeter of wafer, less energy per computation.

A moving, marketed target

Because node labels no longer map to a single measurable dimension, comparing "5 nm" from one foundry against "5 nm" from another requires looking at transistor density and real-world power and performance rather than the headline number. The physics underneath the labels has changed too. Planar transistors gave way to FinFET structures, where the gate wraps around a fin of silicon for better control at small sizes, and the leading edge is now transitioning to gate-all-around (GAAFET) designs. Printing these features at the smallest nodes requires EUV lithography, machines so complex that only a handful exist per fab. Each of these transitions kept Moore's Law limping forward while making leading-edge capacity scarcer and more geographically concentrated.

What the node means for a miner's lifecycle

A chip is committed to a specific node at tape-out, when the finished design is sent to the foundry and the mask set is manufactured; there is no changing it afterward. That decision fixes the machine's efficiency class for its entire service life and shapes semiconductor yield and cost per chip: newer nodes cost dramatically more per wafer, so designers balance efficiency gains against wafer price and maturity. For an operator, the practical consequence is that node generations define the depreciation curve of the fleet. A machine two nodes behind the frontier can still mine profitably where power is cheap or where its heat is the product, which is why older-node hardware keeps finding second lives in heat reuse and home mining long after industrial farms retire it. Efficiency frontiers move; a working hashboard is still a working hashboard.

Node economics also explain the rhythm of the hardware market. A leading-edge wafer costs several times what a mature-node wafer does, and the mask set for a new design at the frontier runs into the tens of millions of dollars, costs that only make sense for chips sold in volume. Mining ASICs are actually well suited to early adoption of new nodes: a SHA-256 core is small, regular, and endlessly repeated, so defects cost little yield compared with a huge monolithic die. That is why mining silicon has repeatedly appeared on a new node within a year or two of the smartphone chips that pay for the fab, and why each node transition triggers a visible generational turnover in the fleets.

See node progression across miners in the ASIC release timeline.