Redistribution Layer (RDL)

A redistribution layer (RDL) is one or more layers of patterned copper traces and dielectric film built directly onto the surface of a die or wafer. Its job is to electrically reroute the chip's native input and output pads, which are usually packed at a very fine pitch, out to a looser, more manufacturable array of connection points. RDLs are a core building block of wafer-level and fan-out packaging, and they quietly determine how many connections a modern chip can actually expose to the outside world.

How it is built

The RDL is formed by depositing alternating layers of organic dielectric, such as polyimide or BCB, and metal, almost always copper. Lithography defines the routing traces, which fan the signals from the dense on-die pads outward to a relaxed footprint where solder balls or bumps can be placed. This is what makes wafer-level chip-scale packages and fan-out packages possible: in a fan-out flow, individual dies are reconstituted into a synthetic molded wafer, and the RDL extends connections beyond the original die boundary to gain more area for I/O than the bare silicon could offer. In effect the package borrows real estate the die itself does not have.

Relevance to advanced packaging

RDLs underpin much of modern heterogeneous integration. They route power and signals across a package, connect multiple dies placed side by side, and in some architectures replace a silicon interposer entirely at lower cost. As mining and AI accelerator silicon pushes toward higher pin counts and tighter pitches, RDL-based fan-out and chip-scale packaging become increasingly important to delivering all those connections reliably. The packaging is no longer an afterthought bolted onto a finished chip; it is a design layer in its own right, and the RDL is where much of that design work happens.

Fine-pitch routing and its limits

An RDL is characterized largely by its line-and-space capability — how narrow a trace it can print and how tightly it can pack neighbouring traces. Finer geometries let more signals escape the die but demand more precise, lower-yielding processes, so there is a constant trade between density and cost. High-end accelerators use several RDL layers stacked up to route the enormous number of power and data connections their dies require, which is one reason their packages are as sophisticated as the chips inside them.

Why it matters downstream

For anyone reasoning about why advanced chips are expensive or supply-constrained, the RDL is part of the answer. Fine-pitch redistribution and fan-out are precision processes with their own yield and equipment bottlenecks, distinct from the wafer fab that made the die, so a perfectly good die can still be gated by packaging capacity. Understanding that the visible package hides several layers of copper doing real routing work demystifies much of the cost and scarcity behind high-end silicon.

It is easy to lose sight of how far packaging has come, so a concrete framing helps: a modern accelerator is less a single chip than a small circuit board built at silicon scale, with the RDL acting as its wiring. The same trend runs through high-performance silicon generally, including the ever-denser control and hashing chips at the heart of mining hardware, where getting hundreds of power and signal connections off a tiny die reliably is a genuine engineering feat. Because these redistribution and fan-out steps happen after the wafer is fabricated, they add their own handling, inspection, and yield-loss stages to a chip's journey. That extra journey is part of why advanced parts carry the prices they do, and why a repair technician will almost never see inside this layer — it is sealed within the package long before a board ever reaches a bench.

See Silicon Interposer for the higher-density routing alternative the RDL sometimes replaces, Flip Chip for the bump attachment RDLs feed, and High Bandwidth Memory for a package where interposer and RDL routing come together.