Semiconductor Yield

Semiconductor yield is the percentage of dies on a finished wafer that function correctly and meet specification. Because a wafer's processing cost is largely fixed — the same hundreds of steps run whether every die works or none do — yield is the single biggest lever on the cost of each working chip: if half the dies fail, every good die effectively pays for a bad one. Yield is therefore central to the economics of every mining ASIC, and it quietly shapes miner prices, availability, and even how firmware handles imperfect silicon.

What drives yield

Random manufacturing defects — a particle landing during photolithography, a void in a via, a short between metal lines — are scattered across a wafer at some average rate, known as the defect density (often written D0). A larger die presents a bigger target, so it is statistically more likely to contain at least one fatal defect. Classic yield models such as the Poisson and Murphy models combine die area and defect density to estimate how many dies survive. As an illustration, a 300 mm wafer carrying 100 mm-squared dies at a defect density of 0.5 per cm-squared yields on the order of several hundred good dies. Beyond random defects, parametric yield matters too: dies can be fully functional but too slow or too leaky to meet spec, failing not because anything is broken but because process variation pushed them outside the target envelope.

Why mining ASICs are built the way they are

This math explains a defining choice in mining silicon: hashing chips are small. Rather than one enormous die, an ASIC vendor prints a compact die and then populates a hashboard with dozens or hundreds of them. Small dies dodge the area penalty — each one is a small target for defects — so more of the wafer survives. Mining chips also tolerate imperfection unusually well: a SHA-256 core array is massively repetitive, so a die with a few dead hashing cores can still ship, recovering silicon that a CPU vendor would scrap. Dies that pass at different speed and leakage grades are sorted downstream through chip binning, which is one reason two "identical" miners can behave differently under tuning.

The learning curve, and what miners feel

Early in a new node's life, yields are low and chips are scarce and expensive; as the foundry refines the process, yield climbs and cost per working chip falls. This learning curve is a large part of why miners of a given generation start dear and soften in price over their production run, and why the first units on a bleeding-edge FinFET or gate-all-around node carry a premium. The economics run backwards through the whole chain: yield determines chip cost, chip cost dominates hashboard cost, and hashboard cost sets the floor under dollars-per-terahash. When you compare an early-run flagship against the same model a year later, part of the price difference is simply the foundry getting better at printing that design after tape-out.

For the home miner and repair bench, yield is also a reminder that silicon is statistical, not identical: every chip on your board passed a test threshold, but each carries its own margins — which is exactly why runtime autotuning per domain outperforms one-size-fits-all settings.

See generational cadence in the ASIC release timeline.