Avalon Series – ECHU Chip Status Code Reference

Pull the full `estats` reply: `echo -n '{"command":"estats"}' | nc <miner-ip> 4028`. Save the reply to a timestamped text file. On Windows without `nc`, use PuTTY in raw mode to `<miner-ip>:4028` and paste `{"command":"estats"}` + Enter. Note the three values inside the `ECHU[a b c]` triplet. The web UI does not expose `ECHU` directly — the API is the only way to read it. This snapshot is your baseline; D-Central's bench team will ask for it if the fix escalates.

Decompose each non-zero `ECHU` value to its set bits. Use a calculator. `ECHU[128 0 0]` = chain 0 has bit 7 set. `ECHU[513 0 0]` = chain 0 has bits 0 + 9 (`1 + 512`) set. `ECHU[129 0 0]` = chain 0 has bits 0 + 7 (`1 + 128`) set. Always decompose; never reason about `ECHU` as a single decimal code. Two faults stacked on the same chain need both repair paths, not just one.

Cross-chain pattern check. `ECHU[N 0 0]` = chain-localised fault. `ECHU[N N N]` = controller-side. `ECHU[N M 0]` = shared-harness or shared-rail fault between two slots. The shape of the triplet tells you whether to start with the boards or the controller, before you open the chassis. This is a 60-second check that saves hours.

Shop-vac the intake filter and wipe the front grille. Dust on the intake raises chip temps regionally and trips bit 7 (`128`, chip-temperature outlier) before it trips any other bit. This is the cheapest fix for `ECHU[128 ...]` patterns and clears a meaningful percentage of bit-7 flags without further work.

Verify intake ambient with an IR thermometer at the front grille — not the middle of the room, not the hallway. Target ≤ 30 C for A11 / A12; ≤ 32 C for A13+. Above 35 C ambient, bit 7 will trip regardless of pad quality or fan health. Fix the room before opening the chassis.

Run a 30-minute slot-swap test for any chain showing `ECHU[N 0 0]` / `[0 N 0]` / `[0 0 N]`. Power off at the breaker. Label slots 0/1/2 with tape. Move the suspect board to a different slot. Power on. Run 30 minutes. Re-pull `estats`. If `ECHU` non-zero follows the board = bad board, move to Tier 3. If it stays in the slot = AUC3 / ribbon / MM control path for that slot. Saves shipping fee on a board that wasn't the problem.

Reseat the AUC3 controller USB cable on A11 / A12 generations. Power off at the breaker first. Inspect AUC3 USB pins for corrosion or blackening before reconnecting. A dab of dielectric grease on oxidised pins has cleared persistent `ECHU[N N N]` patterns on three-year-old A1246s in D-Central's repair queue. AUC3 handshake faults masquerade as chain-level `ECHU` traps until you prove them otherwise.

Reseat the MM-to-hashboard ribbon harnesses on A13+ integrated designs. Power off at the breaker. Disconnect each ribbon, inspect contacts for blackening / oxidation, reconnect firmly. Listen for the click. Re-pull `estats` after each ribbon reseat — a marginal ribbon will show intermittent zero / non-zero `ECHU` across consecutive pulls.

Query `{"command":"version"}` on port 4028 and compare your MM firmware build against the last-known-good at `avalonminer.org/firmware-document/` (A1166 Pro: 20220926 family; A1246: 20230424 family; A13+: most recent stable). If you're on a newer or older build, flash known-good and soak-test 24 hours. Re-pull `estats` — some MM revisions ship `ECHU` reporting bugs that clear on a known-good rollback.

Measure mains voltage under load at the PSU input with a multimeter. Standard Avalon PSUs expect 200-240 V. Sag below 195 V during hash bursts trips bit 0 (`1`) on `ECHU` across all three chains — the cascade looks like multi-chain hashboard fault but is actually a power-environment fault. Dedicated 240 V circuit strongly preferred over 120 V for Avalon-class power draw.

Tune AUC3 IIC bus speed if a slot-localised `ECHU[N 0 0]` persisted through the slot-swap test. Edit the miner config to `--avalon7-aucspeed 200000` (down from the 400000 default), keep `--avalon7-aucxdelay 19200`. A slower bus is more tolerant of marginal cables and noise. Watch the log for `CODE_MMCRCFAILED` events — if they disappear and `ECHU` clears, you had an AUC3 bus-margin problem.

Set DNS to `1.1.1.1` + `8.8.8.8` in the miner network config. Drop Canaan's default `114.114.114.114` Chinese resolver. DNS lag does not directly cause `ECHU` faults, but `GHSavg` lag from DNS-side stratum delay can mask a real `ECHU` chain-degradation pattern by making realized hashrate drop look pool-side instead of chain-side. Clean DNS = cleaner diagnostics.

Refresh thermal pads on any board whose chain shows persistent bit 7 (`128`) — chip-temperature outlier — after Tier 1-2 ambient and filter work. Arctic TP-3 or equivalent, 1.5 mm pad thickness matched to original. IPA 99% to clean old residue. An 8-12 C drop in `PVT_T` is typical on a three-year-old A11 / A12 board and directly clears thermal-driven bit-7 traps. Newer A13+ hashboards use tighter pad specs — match the hashboard revision exactly.

Walk the `PVT_V` array on any chain showing bit 9 (`512`) — chip disabled. Chips on the same board should track within ±20 mV. A chip position reading 0 V or far-drifted is the disabled chip's domain. Cross-reference the chip position with `PVT_T` at the same position. Hot AND drifted = chip degradation, candidate for reflow / replacement. Cold and dropped = LDO / power-domain fault on that chip — may be PCB-level rather than chip-level.

Reflow the chip whose position is flagged by the `PVT_T` / `PVT_V` cross-check. Remove the heatsink, apply flux to the BGA, preheat the bottom side to ~150 C, top-side hot air at 310-330 C for ~30 seconds. Let cool naturally, re-apply thermal paste, reassemble. The A3206 / A3210 / A3205 BGA packages tolerate a reflow cycle well. Run 30 minutes post-reflow and re-pull `ECHU` — the flag should clear if the joint was the issue.

Inspect the MM control board and AUC3 controller (A11 / A12) under a loupe for scorched traces, bulging electrolytics near the hashboard LDOs, corroded USB pins, or cracked MLCCs near the PMIC. Visible damage = Tier 4, not DIY. Photograph the damage for the D-Central repair ticket. Canadian-garage operation through two winters of thermal cycling fatigues solder joints and dries electrolytics; treat 3-year-plus A11 / A12 hardware as MM-vulnerable until inspected.

Stop DIY when: slot-swap shows `ECHU` follows a specific board AND a Tier 3 reflow on the flagged chip position has already failed once, OR `ECHU[N N N]` persists across firmware rollback + AUC3 swap + PSU swap + ribbon reseat, OR `ECHU` bit 9 (chip-disable) recurs at the same chip position within 30 days of a reflow. You're in test-fixture territory. Book a D-Central Avalon repair slot at https://d-central.tech/services/asic-repair/ — 5-10 business day turnaround, Canadian workshop, ships Canada / US / international.

Ship with the pre-fix `ECHU` snapshot and your full `estats` log. Anti-static bags, double-box with ≥5 cm foam on every side. Include a note listing: every observed `ECHU` value across the last week, the bit decomposition, the slot-swap test result if you ran one, MM firmware version string, ambient temp, and your contact info. D-Central's bench process uses the pre-fix snapshot to skip the first 30-60 minutes of diagnostic, which directly saves you repair dollars. Pack for drop: the courier will drop your box at least once — assume it.