Power Gating

Power gating is a chip-level low-power technique that completely cuts the supply voltage to a region of a chip when that region is idle. Where clock gating merely stops a block's switching activity, power gating disconnects the block from its power rails altogether — so it eliminates not only dynamic power but also the static leakage current that otherwise flows continuously through every energized transistor, working or not. In modern process nodes, where leakage is a substantial fraction of total power, that distinction is the whole point.

How it works

A power-gated design inserts large sleep transistors between the shared power rails and the block's local power net — header switches on the supply side, footer switches on the ground side, or both. In normal operation the switches conduct and the block sees nearly full rail voltage; when the power-management controller decides the block has been idle long enough, it opens the switches and the local net collapses toward zero. Nothing inside the block can leak meaningfully, because nothing inside the block is energized. The costs are real and threefold. First, state loss: an unpowered block forgets everything, so any contents worth keeping must be saved beforehand — or preserved in special retention registers that keep a trickle supply. Second, wake-up latency and inrush: recharging the local power net takes time and a burst of current that must be sequenced carefully so it does not disturb neighboring circuits. Third, silicon overhead: sleep transistors must be enormous to pass the block's full operating current with minimal voltage drop, and they consume die area while introducing a small resistance even when on. The engineering rule that falls out is break-even time — a block should only be gated if it will sleep long enough for the leakage saved to repay the energy spent sleeping and waking.

Relevance to mining silicon

A Bitcoin mining ASIC is an unusual customer for this technique, because its defining workload never pauses: the SHA-256 hash cores are meant to run flat out for years, and a core that is idle is a core wasting capital. So power gating in mining silicon is not about napping the hash engines — it belongs to the periphery: interface logic, test and debug structures, and coarse power management, including the ability to depower defective or deliberately disabled sections rather than letting broken circuits leak. The mainstream efficiency lever in miners is different but related: voltage domains. Hash chips are organized into series-connected domains whose shared supply is tuned — per domain, never per chip — by the autotuning firmware, trading frequency and voltage against efficiency at runtime. Both techniques express the same underlying truth of modern silicon: controlling power delivery is controlling the product, and the J/TH figure that decides a miner's fate is won or lost in power engineering as much as in logic design.

The bigger picture

Power gating exists because voltage scaling stopped delivering free efficiency: as transistors shrank past the point where threshold voltages could keep falling, leakage rose exponentially and standby power became a first-class design problem — the story told in our Dennard scaling entry. Alongside its milder sibling clock gating and the underlying phenomenon of leakage current, it is one of the standard weapons chip designers deploy in a war where every nanowatt of waste, multiplied across billions of transistors and years of runtime, shows up somewhere as heat and cost.

The concept also scales up the stack in a way operators will recognize: shutting off an idle hashboard, curtailing a container during a price spike, or cutting a miner over to heat-reclaim duty are all power gating writ large — the same break-even reasoning about sleep duration, state preservation, and restart cost, applied at watts and kilowatts instead of nanowatts. Good power management looks the same at every scale: know what a block costs to keep alive, know what it costs to wake, and never pay for silicon — or machines — doing nothing.