ASIC BGA Reball & Reflow Profile Reference: Lead-Free Rework by Chip

Every other layer of hashboard repair — reading the fault, checking diode values, choosing a test fixture — eventually leads to the same place: a chip has to come off and a new one has to go back on, and that means a reflow curve. This reference is the layer the rest of D-Central’s repair depth was pointing at: the lead-free reflow profile as a staged temperature-and-ramp table, and a per-chip guide to what the Bitmain and Whatsminer ASICs a bench actually reballs demand. It is grounded in D-Central’s own Laval bench practice and the public JEDEC solder standard — and it is scrupulously honest about the difference between a value that is verified and one that varies by board.

Why lead-free changed the rules

Old leaded solder melted at 183 °C and forgave a lot of sins. Modern ASICs use lead-free SAC (tin-silver-copper) solder that doesn’t liquefy until 217 °C, which is why reworking them runs hotter, needs a proper soak to activate flux and equalize temperature, and punishes a rushed ramp with cracked pads and lifted traces. The profile in the table above is the JEDEC J-STD-020 lead-free envelope — preheat, soak, sixty to ninety seconds above the 217 °C melting point, a peak around 235–245 °C measured at the joint, then a controlled cooldown — adapted for the hot-air rework a repair bench actually uses. The single most expensive misunderstanding in this whole process is reading the station’s ~350–380 °C nozzle setting as the chip temperature: air cools between the nozzle and the pad, so the joint is far cooler than the display, and the only way to know the real number is to measure it with a thermocouple or thermal camera.

The profile is common; the geometry is per-board

Here is the honest structure of this dataset. The reflow profile is largely the same across every Bitmain generation because they all use the same class of lead-free solder — so the staged curve applies broadly. What genuinely varies is the board: an S9’s small chip on a thin board is forgiving, while a dense S19 or S21 hashboard is a heavy copper heat sink that will fight your nozzle unless the whole board is preheated from below, and needs the longer end of every soak. And the exact solder-ball count and pitch differ by hashboard PCB revision — so where we can confirm the D-Central bench standard (0.4 mm SAC lead-free balls) we say so, and where the per-revision geometry isn’t publicly pinned down we flag it “verify” rather than invent a false-precise number. The chip-genealogy discipline carries through here too: the BM1396 in an S17e is a different die from the BM1397 in an S17+, and you order the part accordingly.

This is deliberately a reference for trained technicians, not a how-to that pretends reballing is easy — done wrong it destroys the board you were trying to save. It sits alongside the rest of the repair-bench toolkit: the test-fixture selection matrix tells you how to test the board after, the diode & voltage reference gives you the pass/fail values, and the fault localizer tells you which chip to pull in the first place. If you don’t run a hot-air bench — and most people shouldn’t — that is exactly what D-Central’s chip-level repair service in Laval exists to do.