Innosilicon T2T – Hashboard Not Detected

Hard power-cycle the miner at the breaker for 60 seconds minimum. Not a soft reboot and not an SSH `reboot`; physical power removal clears wedged I2C state and wedged-kernel conditions. If the board rejoins the UI on re-boot, you are done — but note the event and schedule a chassis clean within 30 days because the conditions that wedged the controller are usually dust-and-heat related.

Open the chassis and visually inspect the suspect slot. Look for dust on ribbon ends, cable damage (pinched, cut, or chewed), and any heat damage near the `6-pin PCIe` connectors (blackening, brown discoloration, melted plastic). Note but do not touch; photograph everything before anything else. A board with visible heat damage may already be a Seek Professional case before you compound the problem.

Reseat ribbons and power cables on the missing slot. Power off. Disconnect both `6-pin PCIe` power connectors and both signal ribbons on the affected slot. Inspect contacts under bright light. Reconnect firmly — push until you hear the click on the power connectors and feel the ribbon seat fully. Close the chassis and boot. This resolves ~35% of `not detected` cases in D-Central's T2T queue.

Swap hashboards between slots to isolate board-vs-slot. Label slots `0` / `1` / `2` with masking tape first. Move the suspect board to a known-good slot; move a known-good board into the suspect slot. Boot. If the fault follows the board it is a board fault — move to Tier 2 or 3. If the fault stays in the slot it is a control-board or slot-wiring fault — skip to control-board-side work (Tier 3).

Inspect and clean the chassis airflow path. Dust on the intake and on the hashboards raises chip-junction temperature, accelerates solder-joint creep on the fragile chip positions, and causes intermittent drops that look like `not detected`. Shop-vac the intake, wipe the PCBs (power off, grounded, lint-free microfibre, no isopropyl on the chips), clear the fan blades. A clean T2T runs `8–12 °C` cooler on the hashboards than a dusty one.

Multimeter the `12 V` rail at the hashboard `6-pin` connector under load. Probe at the connector while the miner is booting and trying to enumerate. Expect `11.8–12.4 V` sustained. Below `11.6 V` points at PSU sag — go fix the PSU first. Above `12.8 V` is an overvoltage fault — stop immediately before a PMIC cooks. Exactly `0 V` points at a control-board-side buck or fuse failure — that is Tier 3 work.

Reseat every connector in the whole miner, not just the suspect slot. Power off. Disconnect and reconnect every ribbon and every `6-pin PCIe` power cable on all three slots, plus the control-board power input. The T2T is notorious for sympathetic connector-creep: a slot `2` drop can be caused by a marginal contact on slot `0` pulling the harness sideways under thermal cycling. One full-chassis re-seat once a year extends service life.

Inspect every hashboard for visible capacitor failure. Look along the input boost section and near the PMIC for bulging electrolytics (flat-topped caps that have domed up, brown crust at the base), cracked MLCCs, or discoloration indicating heat damage. Any bulged cap means the board needs recapping before re-commissioning — that is Tier 3. Photo-document any damage before proceeding.

Check the control-board-side I2C lines with a scope or multimeter. With the miner powered and the suspect board disconnected, probe `SDA` and `SCL` on the ribbon header — both should idle at `3.3 V` (high). If either line is stuck at `0 V`, the pull-up is blown or the line is shorted to ground. If either line is floating (fluctuating voltage), the control board I2C buffer is damaged. Either finding means Tier 3.

Swap ribbon cables with known-good. Ribbons are the cheapest failure point on a T2T and they fail silently — a cracked conductor inside the insulation shows no visible damage. D-Central keeps a drawer of pull-good T2T ribbons; if you run a T2T fleet, so should you. Swap, boot, observe. Restore confirmed-bad ribbons to the recycling bin, not the spares bin.

Pull the board to the bench and read its EEPROM. ESD mat, CH341A programmer + SOIC-8 EEPROM clip (or equivalent), locate `U6` on the board, read the EEPROM contents. Expected: a readable Innosilicon calibration header. Observed: `0xFF` fill (blank), `0x00` fill (corrupted write), or read-fail (dead EEPROM). Blank or corrupted: re-flash from a known-good image matched to the board's voltage-domain revision. Read-fail: the EEPROM is dead — desolder and replace.

Thermal-image the board during boot enumeration. Power the board via the control board (or a bench fixture simulating the enumeration sequence). Point an IR camera at the chip array during the first 60 seconds. Normal chips rise to `45–55 °C` evenly. Fragile-position chips on a failing T2T board show `20 °C+` hotter than the average within seconds. Record the positions. On T2T, positions near chip `17`, chip `29`, and the input-side voltage domain are the statistically common culprits.

Control-board-side fault: swap the control board or repair the I2C path. If Step 4 isolated the fault to a specific slot regardless of board, the I2C mux, a pull-up resistor, or the slot's `12 V` buck on the control board is damaged. Control board swaps are the cleanest fix when you have a known-good spare. Repair is possible — pull-ups are standard `4.7 kΩ` `0402`/`0603` parts, muxes are commodity — but requires schematic reference; bench work, not field work.

Reflow the fragile-position chip. Remove the heatsink, flux the BGA perimeter, preheat the board bottom-side to `150 °C` on a preheat plate, top-side hot air at `310–330 °C` for `25–35 seconds`, hold, cool naturally on the preheat, re-apply thermal paste (Arctic MX-6 or Kryonaut), reseat heatsink. Re-enumerate. If the board returns you have bought 6–18 months; if it does not the chip is silicon-dead and needs replacement.

Recap the input boost section if Tier 2 Step 8 found bulged electrolytics. Standard parts are `470 µF` / `1000 µF` at `16–25 V`, low-ESR, `105 °C` rated — match originals or upgrade to polymer equivalents at the same capacitance and voltage. Not a beginner soldering job: tight-pitch layout, ground-plane heat-sinking that demands a decent iron (`60 W+`) and patience. Clean flux residue thoroughly before re-commissioning.

Stop DIY and ship to D-Central if any of: EEPROM read fails (dead EEPROM), multiple chips hot-spot simultaneously, PMIC or voltage-domain MOSFET visibly damaged, reflow returned and the board failed again inside 30 days, capacitor bulging on more than one board (systemic aging). You are now in test-fixture territory. Book a D-Central ASIC Repair slot at https://d-central.tech/services/asic-repair/.

D-Central bench process on Innosilicon T2T: full-board incoming inspection (thermal, electrical, connector), EEPROM read + repair against an archive of known-good T2T images, per-chip I2C isolation via a bench control-board fixture, chip replacement from salvaged-grade T2T stock, PMIC / MOSFET / cap replacement as needed, full post-repair burn-in at nameplate for 24 hours before shipment back. One of the few Western benches still actively repairing Innosilicon hardware.

Ship safely. Pack each hashboard individually in anti-static bags, sandwich between foam, double-box with `5 cm+` of padding on every side. Include a written note with observed symptoms, the specific slot that failed, every Tier 1-3 step you already tried, firmware version, and your contact. T2T boards are fragile freight — we see more boards killed in shipping than in their original failure mode. Over-pack rather than under-pack.