Antminer – Control Board Clock Drift

SSH into the miner and run `date` plus `date -u`. Compare against a trusted UTC source (phone, laptop, `time.is`). Drift under a minute and stable means you're probably not looking at a clock-drift bug — re-check the symptom you opened this page for. Drift over a minute, or a system date in 1970 or a manufacture year, confirms you're in the right place; continue to step 2.

Reboot the miner cleanly. A clean reboot forces the kernel to re-read the RTC and re-trigger the NTP init script, which resolves about a third of clock-drift tickets because a wedged `busybox ntpd` from weeks ago gets a fresh start. Wait 5 minutes after reboot, then re-check `date`. If drift is gone, move to step 5 to harden against recurrence.

Force a manual NTP resync from shell: `ntpdate -u pool.ntp.org` where available, or `busybox ntpd -n -q -p pool.ntp.org -p time.cloudflare.com -p time.google.com`. On Bitmain stock firmware the default `ntp.bitmain.com` is frequently unreachable outside China — overriding with public pools usually fixes drift in seconds. Watch the output for an offset report.

Set the correct timezone on the miner. A number of 'clock is wrong' tickets are actually timezone misconfigs where UTC is right but the UI renders in the wrong zone. On rooted firmware: `export TZ='America/Toronto'` (or your local IANA zone), then persist via `/etc/profile` or the firmware's equivalent. Doesn't affect mining — just log-reading ergonomics.

Check Bitmain firmware version against known-buggy range. Stock builds between roughly 2020-09 and 2022-04 on S17/S19 hardware shipped a `busybox ntpd` with a re-arm bug after network loss. Roll forward to the latest stock for your hardware revision at `support.bitmain.com/downloads`, or flash DCENT_OS / Braiins OS+ / LuxOS to eliminate the bug class entirely.

Add a cron-driven NTP resync. If you must stay on a specific stock firmware, run `crontab -e` on the rooted control board and add: `0 */6 * * * /usr/bin/ntpdate -u pool.ntp.org time.cloudflare.com > /dev/null 2>&1`. This papers over the wedged-daemon bug every 6 hours. Not the right fix, but operational — graduate to a DCENT_OS flash when you can.

Unblock outbound UDP 123 on your network. On pfSense, OPNsense, Unifi, or similar, IoT and VLAN-isolated miners often have UDP blocked by default. Allow outbound UDP 123 to `pool.ntp.org` and `time.cloudflare.com`. On corporate networks where you can't change rules, stand up a local NTP server (`chrony` on a Raspberry Pi, CAD $50 one-time) and point the miner at the LAN address.

Measure the CR2032. Power off at the breaker, let the board cool 15 minutes, remove the control board (Phillips #2, four screws on most variants; Torx T8 on S21). Probe the coin cell with a multimeter in DC V: positive on the flat side, negative on chassis ground. Healthy: 2.9 to 3.2 V unloaded. Replace at under 2.6 V. On a 4+ year old S19/S17 at sustained 55–65 C CB temps, assume at least marginal.

Replace the CR2032. Panasonic, Energizer, or Murata from any hardware store, CAD $2–4. Slide old out, slide new in with + facing up (flat side up on standard holders). Power back on, let NTP resync, then power-cycle once more and verify the clock holds across the cold boot. Single highest-ROI preventive-maintenance move on an aged Antminer — CAD $3 of battery saves CAD $200+ of misdiagnosed 'control board dying'.

Verify RTC write after battery replacement. With the fresh cell installed and the system clock correct (NTP has just resynced), run `hwclock --systohc` (or firmware equivalent `hwclock -w`) to force the kernel to write current system time into the RTC IC. Some firmwares don't do this automatically and the RTC keeps the old wrong time despite the new battery. Power-cycle once more and confirm the clock holds.

Flash DCENT_OS for proper time management. DCENT_OS is D-Central's own open-source Antminer firmware — `systemd-timesyncd` with configurable pools, proper NTP step-slew behaviour, plus all the per-chip HW% and tuning features of Braiins OS+ / LuxOS / Vnish, open-source on GitHub. Alternatives: Braiins OS+ (`chrony`), LuxOS (`chrony`), Vnish. All four kill the stock wedged-ntpd bug permanently. Flash via SD-card-recovery path for your specific hardware revision.

Run a local stratum-1 NTP server. For fleets of 2+ miners or firewalled networks you don't control, a Raspberry Pi 4 running `chrony` with a GPS PPS hat gives microsecond-accurate LAN NTP for under CAD $150 one-time. Point every miner at its LAN address — Antminers, Whatsminers, Avalons, and Bitaxes all benefit from a single known-good local time source. Standard professional-farm setup.

Probe the I2C bus to the RTC IC. If the battery is fresh and cold-boot drift persists, the RTC IC may be failing. Power the CB on the bench, put a scope on SDA and SCL lines to the RTC (RX8025T, DS1339, or PCF8563 depending on revision). Expect I2C activity at boot as the kernel reads the RTC. Flat lines or stuck-low lines indicate a bus problem. SDA stuck low can sometimes be cleared by pulsing SCL nine times; if it re-locks, the RTC IC itself is bad.

Replace the RTC IC. Chip-level work, hot-air required. Source exact PN from Digi-Key or Mouser, CAD $3–8 per chip. Flux, hot air at 260–290 C, lift the old chip, clean pads with IPA, place new chip aligned to pin 1, reflow. After reassembly boot and check `dmesg | grep rtc` for a clean driver init, then `hwclock --systohc` to seed the new IC with current time.

Cross-check firmware TLS CA bundle. If your clock is correct but TLS pools still refuse handshakes, the firmware's baked-in CA bundle may have expired (common on 2020-era firmware running into 2026). Flash newer firmware, or install an updated `/etc/ssl/certs/ca-certificates.crt` from Let's Encrypt or `curl.se/ca/cacert.pem` via SFTP. This sub-bucket chains with clock drift in ways that confuse operators until they see it once.

Know when to stop DIY. Two scenarios trigger Tier 4: (a) fresh CR2032 verified >2.9 V AND the clock still resets on every cold boot — something deeper is wrong (trace damage, failing SoC RTC domain, cracked crystal); or (b) you don't want to do chip-level work and battery replacement didn't fix it. Photograph the board, gather the context (firmware version, drift pattern, what you've tried), and book a D-Central ASIC Repair slot at https://d-central.tech/services/asic-repair/.

D-Central bench process for RTC drift: scope-verify I2C traffic to the RTC, measure crystal oscillation on a spectrum analyzer, replace RTC IC or 32.768 kHz crystal as required, re-seat or re-solder battery holder (a cracked solder joint on the holder pin — not the battery itself — is a common root cause we see), 24-hour soak-test with two full power cycles to confirm the clock holds. If the board is truly dead we swap from graded inventory and migrate firmware/config so you don't lose OC profiles.

Ship safely. Control board only — leave hashboards at home. Anti-static bag, wrapped in foam, inside a padded box. Include a note with: observed drift behaviour, firmware version, last known-good date, whether the CR2032 has been replaced, what Tier 1–3 steps you've already run, and your contact. Canadian shipping is fast from anywhere in Canada; US and international welcomed. Clear notes save diagnostic time and your repair cost.