Controlled Impedance

Controlled impedance is the practice of designing a PCB trace so its characteristic impedance stays within a specified tolerance of a target value, most commonly 50 ohms single-ended or 90 to 100 ohms differential. At the data rates inside a modern ASIC miner's control board, copper traces behave as transmission lines: if the impedance a signal sees changes abruptly, part of the signal reflects back toward the source, corrupting the waveform. Holding impedance constant keeps reflections small and edges clean.

What sets the impedance

The value is fixed by physical geometry, not by a component. It depends on the trace width and copper thickness, the height of dielectric between the trace and its reference plane, and the dielectric constant (Dk) of the laminate. A fabricator hits the target by adjusting trace width for a given stackup, then often verifies it with a test coupon measured by TDR (time-domain reflectometry). Designers usually request impedance control explicitly on the fabrication drawing, because the board house must tune etching and layer spacing to comply.

Why it matters in mining hardware

Hashboards and control boards carry high-speed clock and data lines between the SoC, PLLs, and ASIC chains. Uncontrolled impedance shows up as edge ringing, timing errors, and intermittent hashboard faults that are hard to diagnose in the field. Repair work that reworks a connector or adds a jumper wire can locally disturb impedance, so signal-critical lines should be kept short and over a continuous reference plane.

For related signal-integrity concepts see differential pair and ground plane.