Bitaxe Supra 400-series open-hardware board and firmware boundary
Open-hardware board reference with exact ASIC family, DC-input and revision-scoped firmware boundaries.
Full Specifications
| Model | Bitaxe Supra 400-series open-hardware board and firmware boundary |
|---|---|
| Model Number | Bitaxe Supra 400-series |
| Manufacturer | Bitaxe |
| Algorithm | SHA-256 |
| Chip Model | BM1368 |
| Chip Count | 1 |
| Cooling | Air |
| Voltage Range | 5V DC (barrel jack 5.5x2.1mm) |
| Operating Temperature | 0-50°C |
| Interface | WiFi |
| Status | Lifecycle not independently verified |
Bitaxe Supra 400-series entity boundary
The dedicated schematic/BOM identifies BM1368; stale repository prose mentioning BM1366 is not used.
This is an open board design licensed under CERN-OHL-S-2.0, not one fixed retail appliance. Multiple assemblers may use different heatsinks, fans, enclosures, displays, adapters, clocks and voltages. Generic retail ProductModel, fixed-SKU comparison and profitability are therefore withheld.
Supra DC and cooling contract
5 V DC only, adapter above 15 W, 5.5 × 2.5 mm center-positive barrel. Active cooling with a 5 V 40 mm fan is mandatory.
AxeOS/ESP-Miner firmware safety
Firmware and factory images must match device-reported board, family, ASIC, ASIC count and hardware revision. Unified releases do not authorize a generic cross-flash; Hex variants may use different maintainer forks. Recovery can leave an incompatible old web partition, so exact release assets and rollback steps are required.
Performance is configurable and autotuned. Voltage/frequency unlocks can damage inadequately cooled hardware. Absolute dBA, assembly dimensions, mass, earnings and “lottery” success are not board-global specifications.