DCENT_OS for Antminer S9

Current answer

A signed sysupgrade package and bootable SD image are downloadable for the S9 Zynq/XIL lane. Accepted-share mining is documented, but the public platform matrix still classifies the installation route as lab-gated.

Artifact and source evidence

Readiness comes before download. Review the dated hardware-status ledger and the recovery-first checklist before taking an artifact. The files below exist on D-Central's download host; each package contains an Ed25519-signed manifest and the directory publishes SHA-256 checksums.

• S9 XIL signed sysupgrade (.tar)
• S9 XIL bootable SD image (.img)
• SHA256SUMS.txt

Primary project evidence: per-model platform matrix, four-tier testing protocol, and GPL-3.0 source repository.

Dated evidence ledger

What the status does — and does not — prove

Mining evidence answers whether DCENT_OS has produced accepted pool shares on named hardware. Install readiness answers whether a general operator can safely move from the original firmware to this build and recover. Those are independent questions.

• Mining verified means accepted shares, not merely detected chips or nonce flow.
• Guarded artifact means a signed file is downloadable but an install, boot, soak, or recovery proof is still incomplete or unpublished.
• Lab-only means the source or runtime path has evidence without a general public installation route.
• In development means there is no public artifact for operators to flash.

Known limitations

• Only the named Zynq/XIL lane has a downloadable artifact; BB, CV and AML labels are not interchangeable.
• The public repository still asks for a witnessed install, boot, mining and recovery capstone before the route is called generally validated.
• No independent stock-versus-DCENT_OS benchmark dataset is published on this page yet.

Do not infer support from the miner name alone. Identify the exact control board, keep a known-good SD/UART recovery path, and never test experimental firmware on revenue-critical hardware.

Identify the exact control board

Use the ASIC control-board reference and physical board markings before interpreting this page. Connector shape, miner family and an ASIC generation are not sufficient identifiers. No stock photo or simulated dashboard is presented as proof for this lane.

Artifact-to-evidence receipt

Test this exact lane and publish success or failure. A report must identify the model, board, artifact digest, source/build state, raw logs and recovery outcome.

Installation and recovery policy

Start with recovery, not features. Read the rollback and UART recovery guide and the hardware-readiness checklist. A dry run should identify the model, board family, route and backup state before any persistent write.

The separate S9 SD-card guide documents the removable-media path. Treat it as experimental until the repository's public capstone is closed.

Performance data

No independent stock-versus-DCENT_OS benchmark dataset is asserted here. D-Central will publish hashrate, wall power, J/TH, thermals, fan RPM, reject rate and stability data only with the raw measurements, hardware identifiers, build commit, pool-side proof and test duration attached. See the benchmark and reproduction protocol.