ASIC Troubleshooting Cheat Sheet — Antminer Bench Diagnostics

This cheat sheet covers Antminer S9 through S21 XP. All specifications are drawn from verified hardware documentation and reverse-engineering research. For full repair procedures and cost guidance see /asic-repair/, /asic-fault-finder/, and /asic-troubleshooting/.

Symptom → cause triage table

Voltage domain sequence and measurement procedure

ASIC chips are not individually voltage-controlled. They are grouped into voltage domains — clusters sharing a single regulated rail from an LDO (low-dropout regulator) or buck converter. This is a critical diagnostic distinction: a fault reads as an entire domain failing, not a single chip’s voltage changing.

Model-specific domain reference

Step-by-step domain voltage measurement

1. Disconnect all power. Wait 30 seconds for capacitor discharge before probing. Large filter caps on boost rails hold dangerous charge.
2. Anti-static setup. Place board on a grounded anti-static mat. Wear an ESD wrist strap bonded to the mat.
3. Unpowered domain impedance check. Set multimeter to 200 Ω resistance range. Black probe to PCB ground test pad (not the heatsink — see caution below). Red probe to each domain VDD test point sequentially. Low impedance outlier = domain short circuit.
4. Power via test fixture. Connect to Bitmain V2.1/V2.3 test fixture or bench supply. Wait 2–5 minutes for stabilization before measuring live voltages.
5. Live domain voltage sweep. Set multimeter to DC millivolt range. Measure VDD1V2 (1.2 V rail) and VDD0V8 (0.8 V core) at each domain test point. All readings should be within ±50 mV of each other for a healthy board.
6. Interpret outliers. 100+ mV below average = partial short (failed chip or blown capacitor). Significantly above average = open circuit (broken trace, cracked solder joint, dead LDO in open-circuit failure mode).
7. Verify boost output. Measure at the output capacitor of the boost converter. Expected voltages are model-specific (see table above). If boost is absent: check the boost MOSFET, inductor, and boost IC.

LDO structure (S21 / S21 XP)

On BM1368 and BM1370 boards, each domain uses three LDOs:

• 1× LDO: Boost → 1.2 V (VDDIO / signal level)
• 2× LDO: 1.2 V → 0.8 V (VDD core)

Domains 11–12 (S21) and 12–13 (S21 XP) are high-voltage domains fed through MP2019 buck converters before the LDO chain. If these specific domains show no output, check the MP2019 (S21: U166/U200; S21 XP: U146/U202) before assuming an LDO failure.

Signal chain reference

Five critical signals on the 18-pin ribbon

Level shifters

The control board operates at 3.3 V logic. ASIC chips use lower signal voltages (1.8 V on S19, ~1.1 V on S21). Level shifters translate these at the board edge and at domain boundaries where voltage changes occur across the chain:

• S21 (BM1368): 11 level shifters total. Shifters 0–9 powered by domain voltages (~6 V cross-domain differential). Shifters 10–11 powered by U118 (19 V boost LDO).
• S21 XP (BM1370): 12 level shifters (U1–U12). U1–U9 domain-powered; U10–U11 powered by U24 (19 V boost).
• S19 series: 2 level shifters at board edge only (3.3 V ↔ 1.8 V). No intra-chain level shifting.

A failed level shifter presents identically to a dead chip at that domain boundary — partial chip count with the break exactly at a domain boundary is a strong indicator of level shifter failure, not a chip failure.

Bench diagnostic sequence — interactive checklist

Check off steps as you work. Progress is saved locally in your browser.

• 1. ESD setup: anti-static mat grounded, wrist strap bonded, board on mat.
• 2. Visual inspection (10× loupe): burnt components, missing SMDs, cracked crystal Y1, damaged connector pins, solder bridges.
• 3. Heatsink check: all clips intact, thermal paste coverage adequate, no delaminated fins.
• 4. Unpowered resistance: measure across main power input connector. Near-zero = hard short on power bus — do not power until resolved.
• 5. Domain impedance sweep (unpowered, 200 Ω range): probe each domain VDD test point vs PCB ground pad. Record outliers.
• 6. Connect to test fixture. Wait 2–5 min stabilization. Measure boost output voltage (see model table above).
• 7. Live domain voltage sweep: VDD1V2 + VDD0V8 at every domain. Mark any reading ≥100 mV outside the median.
• 8. Run PT1 chip enumeration. Note count vs expected (e.g. 108 for S21). If partial, proceed to binary search (step 9). If 0, proceed to CLK check (step 10).
• 9. Binary search fault isolation: short RO test point at chain midpoint to VDD. If count increases → fault is in second half. Bisect until the exact break is found.
• 10. CLK check (if 0 chips): oscilloscope on CLKI test point at chip 1. Expect 25 MHz square wave. Absent = crystal Y1 or CLK trace failure.
• 11. PIC check (S19 series only — skip for S21/T21/S21 XP): measure pin 2 of U3 (S19) or U6 (S19 Pro). Expect 3.3 V. If absent, reprogram with PICkit3.
• 12. EEPROM verify: read with CH341A. Data must match across all three hash boards in the unit. Mismatch or corruption → reprogram from a known-good board’s dump.
• 13. Repair (chip replacement, LDO swap, reflow, or passive component replacement as indicated by findings above).
• 14. Re-apply thermal paste (Fujipoly SPG-30B or equivalent) if heatsink was removed. Even, thin, full-coverage layer on all chips.
• 15. Full re-test: PT1 → PT2 → PT3 in sequence. Repaired boards must pass all three stages before release. Do not skip the test sequence.

Common Antminer gotchas — things that waste bench time

1. There is no per-chip voltage control. Voltage is regulated at the domain level — one LDO (or buck converter) per group of 2–10 chips. A multimeter reading “different voltages per chip” is measuring the cumulative voltage drop across serially-wired chips within the domain, not individual chip control. When documentation says a domain voltage is ~0.36 V (S19) or ~1.2 V (S21), that is the regulated supply for the entire group, not a per-chip target.
2. S21 / T21 have no PIC chip. Bitmain removed the PIC microcontroller starting with the BM1368 generation. The S21 and T21 hash boards do not have U3/U6 PICs. Searching for a PIC on these boards, or expecting a 3.3 V PIC output line, is a diagnostic dead end.
3. S19 Pro has 114 chips, not 76. The S19 has 76 chips (38 domains × 2 chips). The S19 Pro has 114 chips (38 domains × 3 chips per domain) with a lower per-domain voltage (~0.32 V vs ~0.36 V). Mixing up these counts leads to false “partial chain” diagnoses.
4. Probing the heatsink as ground will damage the board. The heatsink is not isolated from the board’s copper planes. Connecting a multimeter’s ground probe to the heatsink creates a short-circuit risk across power rails. Always probe a dedicated PCB ground test pad.
5. A domain-boundary partial count is usually a level shifter, not a dead chip. If chip enumeration breaks exactly at a domain boundary (e.g., 9/12, 18/21), inspect the level shifter at that boundary before replacing any ASIC. Level shifter ICs are considerably cheaper and faster to replace than BGAs.
6. The CLK crystal is 25 MHz, not a tunable parameter. Y1 is a passive 25 MHz crystal oscillator. The hashing frequency is set via PLL registers inside each chip — the crystal provides only the base reference. A failed crystal (cracked package, cold solder on loading capacitors) produces 0 chips detected, identical to a dead first chip.
7. Zynq control board CPU runs at 667 MHz, not 700 MHz. The Xilinx Zynq 7010 (XC7Z010) Cortex-A9 cores run at 667 MHz in Antminer control boards. This matters if you are patching firmware timing loops or building third-party control software.
8. EEPROM data must match across all three hash boards. Hash boards are calibrated as a matched set. Installing a replacement board with different EEPROM data causes the control board to reject it or produce anomalous hashrates. Always read and verify all three EEPROMs before a final assembly test.
9. S19 XP domain count is 11, not 38. Unlike the S19 / S19 Pro (38 domains), the S19 XP uses BM1366 chips in a different topology: 110 chips across 11 domains (10 chips per domain, ~0.40 V each). Applying S19 domain voltage expectations to an S19 XP leads to wrong fault conclusions.
10. Repaired boards must run PT1 → PT2 → PT3 in sequence — no skips. PT2 (pattern test) only makes sense after PT1 (chip enumeration) passes. PT3 (frequency sweep) requires the heatsink fully assembled with fresh thermal paste and fans running. Skipping steps results in boards leaving the bench in an untested state.

PSU quick reference

Frequently asked questions

How do I find which chip is breaking the signal chain without a commercial tester?

Use the binary search (dichotomy) method. When chip enumeration reports fewer chips than expected (e.g., 53 of 108), the chain breaks between the last detected chip and the next one. Short the RO test point at the midpoint of the chain to VDD (the domain voltage at that point). Run enumeration again. If the count increases, the fault is in the second half; if the count stays the same or decreases, the fault is in the first half. Continue halving the search space until you reach a single chip. This technique works because injecting a high signal into the reverse chain at a bypass point simulates a valid nonce response from that position, making all healthy downstream chips visible.

Why does my S21 show a different chip count every time I run PT1?

Intermittent chip enumeration on an S21 typically indicates a BGA cold solder joint on one of the chips near the break point (thermal cycling causes micro-cracks that open and close with temperature). It can also indicate a failing level shifter — S21 boards have 11 level shifters, and a marginal one can pass or fail depending on temperature and supply voltage at the moment of enumeration. Thermal camera imaging under load (heatsink removed for a brief run) usually pinpoints the failing component as a cold spot surrounded by active chips.

Can I use an S19 Pro hash board in an S19 chassis?

The physical form factor and connector are the same, but the EEPROM data and voltage calibration are board-specific. An S19 Pro board (114 chips, 38 domains × 3) in an S19 chassis (expecting 76 chips, 38 domains × 2) will enumerate a partial count and the control board firmware may reject it or apply wrong voltage settings. Mixing is not recommended without EEPROM re-calibration. Always keep matched sets (all three boards with consistent EEPROM data from the same production batch).

What is the first thing to check when the boost voltage is absent?

With the board unpowered, measure resistance between the power MOSFET pins (gate, source, drain — pins 1, 4, 8). A near-zero reading between any two pins indicates a failed MOSFET (shorted in breakdown). If the MOSFET tests clean, check the boost inductor for continuity (an open inductor produces zero boost output), then the boost controller IC for supply voltage. Pre-built replacement boost module boards are available for S19 and S21 series and replace the entire burned circuit including any damaged PCB pads.

How do I tell the difference between a failed LDO and a failed ASIC chip in a domain?

Unpowered, measure impedance at the domain VDD test point versus board ground. Very low impedance (near zero) with no obvious chip damage on visual inspection suggests the LDO output capacitors or the LDO itself is shorted — LDO failures typically produce a hard short that registers before any chip can be assessed. A chip failure is more likely if impedance is normal unpowered but the domain voltage is abnormal under power. When in doubt, remove the LDO (small SMD IC, 4-pin SOT package) and re-measure — if impedance normalises with the LDO removed, the LDO is the fault.

Do I need a Bitmain test fixture, or can I use the miner itself for diagnostics?

The miner’s own control board exposes diagnostic data via its CGMiner/bmminer API on port 4028 and via kernel sysfs paths. You can read chip counts, chain status, and temperature sensor data without any external fixture — useful for triage and initial fault isolation. For PT2 (pattern test) and PT3 (frequency sweep), a Bitmain V2.1/V2.3 test fixture or a third-party tester (such as ARC, STASIC, or K3L/K8) provides more reliable and repeatable results than in-miner testing, and lets you test hash boards independently of a control board.

Go deeper

• Full ASIC troubleshooting guide — extended diagnostic walkthroughs for each failure category
• ASIC repair service — professional board-level repair options
• ASIC fault finder — interactive symptom-based fault identification tool
• Repair cost estimator — estimate repair vs replace economics before sending a board for service
• ASIC chip reference — full BM-series chip specifications (BM1387 through BM1370)
• PSU repair guide — APW-series fault diagnosis and repair procedures
• Field manual — operational procedures and site-level troubleshooting
• Mining academy — foundational Bitcoin mining technical education