How to fix “crc check error” on Bitmain Antminer L3+ ASICs

A crc check error on an Antminer L3+ means a frame came back off the chain and its checksum did not match — the chip answered, but a bit flipped between the die and the control board. This is a signal-integrity fault, not a dead chain. The board still enumerates and cgminer keeps dispatching work, so the miner draws its full ~800 W while hardware errors climb and accepted hashrate falls well under the 504 MH/s nameplate. You pay for a whole miner and get a fraction of one — and the marginal joint behind it usually degrades into a dead chain.

What the error actually reports

Each L3+ hashboard carries 72 BM1485 chips (4 boards, 288 total) on a shared UART daisy-chain. Commands flow forward CI → CO; responses return RO → RI. Every frame is checksummed:

• Register frames — a read is 5 bytes, 0x42 0x04 <chip_addr> <reg> <CRC5> (broadcast 0x52); a write is 9 bytes (0x41 / 0x51). CRC5 covers 32 and 64 bits respectively.
• Nonce response — 7 bytes: header, 4-byte nonce, chip address, CRC5. Bare bytes: the BM1485 uses older BM1387-style framing with no 0x55 0xAA preamble (bitmain-use-vil is not set on the L3+).
• Work frame — ~86 bytes carrying the full Scrypt block header rather than a SHA-256 midstate, protected by CRC16 rather than CRC5.

The BM1485 tracks corruption itself in MISC_CONTROL (register 0x18) through three flags: cmd_crc_err, work_crc_err, gap_crc_err. Corruption runs both ways — the chip can reject what the host sent, the host can reject what the chip returned — and both indict the same physical wire.

Separate this from its neighbours. Find 0 asic means nothing answered: dead chain, no reset, no clock, open CI line. Lacks chips means enumeration stopped at a partial count: a hard break mid-chain. A CRC error means the chain answered and answered wrong — a narrower, far more repairable fault.

One caveat governs everything below: CRC5 is a 5-bit checksum over a 7-byte response. It is weak. A chain bad enough to log CRC errors is also silently passing corrupt nonces through as hardware errors. “The CRC lines stopped” is not proof of health.

Likely causes, ranked

1. The signal cable. Ribbon cables age, vibrate loose, corrode at the crimp. Most common, cheapest to rule out.
2. Cold or cracked joints on a BM1485’s CI/CO/RO/RI pins, or on the series passives between chips. One high-resistance hop degrades every chip downstream.
3. Baud margin. The chain boots at 115,200 bps, then upgrades: BaudRate = 25 MHz / ((bt8d + 1) × 8) — bt8d=7 gives 390,625 bps, bt8d=1 gives 1,562,500 bps. Enumeration happens at the slow boot rate; CRC errors appear after the upgrade, when timing margin collapses. That is why a board counts 72/72 chips and still fails.
4. A sagging 12 V rail. The L3+ ships with a 12 V Bitmain supply (APW3-class or APW7), spec’d 11.6–13.0 V DC, and pulls ~800 W at nameplate. On 120 V those units derate — an APW7 to ~1000 W, an APW3++ to ~1200 W — so headroom is thin, and gone once the unit is tired.
5. Thermal. Clean cold, erroring hot: dust, a stalled fan, a lifted heatsink.
6. A weak 25 MHz reference. One clock feeds the PLL (freq = 25 × FBDIV / (REFDIV × POSTDIV1 × POSTDIV2)) and the UART bit rate, so a dirty clock corrupts every chip on the board at once.
7. A single failing BM1485, or a droopy domain feeding six of them. Last on this list, not first.

Diagnose before you desolder anything

Pull the kernel log and read the pattern, not just the presence of errors. BM1485 addresses are assigned sequentially 0–71 (the BM1387 steps by 4; the BM1485 does not), so a flagged address indexes straight into the chain.

• Errors repeating on one address → that chip, its joints, or its domain.
• Errors scattered across the chain → cable, clock, power, or a cold joint near the head of the chain.
• Swap the signal cable with a known-good chain’s. If the fault follows the cable, you are done in two minutes.
• Move the hashboard to another slot. Fault follows the board → the board. Fault stays with the slot → control board, cable, or that slot’s 12 V feed.
• Drop the frequency. L3+ steps (384 MHz nameplate confirmed; the lower steps are the documented undervolt profile — expect small variance unit to unit): 384 MHz / 10.0 V (nameplate, 504 MH/s), 320 MHz / 9.8 V (~432 MH/s), 270 MHz / 9.6 V (~360 MH/s). If CRC errors vanish at 320 MHz and return at 384, the chain is marginal — which means repairable.
• Cold start vs. hot soak. Errors that only appear 20 minutes in are thermal until proven otherwise.

Electrical measurements

Safety: the hashboard’s DC side is low-voltage — the string runs under 11 V, each domain under 1 V. It is not a shock hazard. The PSU is. Its mains side holds roughly 400 V on the PFC capacitors after you unplug it. Measure the DC side; leave the PSU casing shut.

1. 12 V at the hashboard connector, under load. Expect 11.6–13.0 V. A rail that sags only while hashing indicts the PSU, the cable, or an oxidised connector — not the board.
2. String voltage across the chip chain. The 72 chips sit in a series string: expect ~9.6–10.2 V by frequency step (10.0 V at the 384 MHz nameplate). Out of band means regulation, not silicon.
3. Walk the 12 voltage domains. Each is 6 chips sharing one regulated rail. Scale the expectation to the string voltage you actually measured: ~0.80 V per domain at the 9.6 V (270 MHz) step, ~0.83 V per domain at the 10.0 V nameplate step. Core range is 0.6–0.8 V nominal. Regulation on the L3+ is per domain, never per chip. A domain reading low, high, or near zero localises the fault to those six chips.
4. The 1.8 V IO rail. This is what the UART signalling swings against. A sagging or noisy VDDIO is a textbook CRC generator while the chips still enumerate perfectly.
5. The 25 MHz crystal. Scope frequency and amplitude — it clocks the PLL and the UART both.
6. The RO/RI return line, under load. Scope the response line at the head of the chain at post-upgrade baud; a slow edge or a few hundred millivolts of ringing will flip a bit.
7. RST. It reaches the chain from a control-board GPIO through a level shifter — confirm it asserts and releases cleanly on start.

Board-level repair

• Reflow before you replace. Preheat, flux, reflow the flagged chip’s UART pins plus the passives on its CI → CO and RO → RI hops. Cracked joints are the highest-yield fix on a CRC-erroring L3+ board.
• Check the hop passives. An open or high-resistance series component between two chips degrades everything downstream — and reads exactly like a bad chip in the log.
• Replace the BM1485 only when reflow fails. Then re-measure that domain’s rail: a shorted chip drags its domain down and takes five neighbours with it.
• If the whole string is out of band, suspect the voltage-setting path. On the L3+ the chain voltage is set from the control board per chain (GPIO-driven), not per domain — twelve domains do not drift together by coincidence.
• Do not hunt for a per-chip voltage trim. It does not exist. Granularity is the 6-chip domain.

Verify the fix

1. Run the 384 MHz / 10.0 V nameplate step and confirm ~504 MH/s at ~800 W. A board that is clean only at 320 MHz is masked, not repaired.
2. Watch hardware errors, not just the log. Because CRC5 is 5 bits, a chain can pass the checksum and still corrupt nonces. Compare pool-accepted against reported hashrate over several hours; a persistent gap means the chain is still marginal.
3. Soak it hot and re-check once the board has held full load to steady-state temperature.

Common mistakes

• Reflashing firmware. A reflash fixes a corrupted image, not a corrupted frame. If the chain counts 72/72 and then throws CRC errors, the software is fine and a wire is not.
• Confusing it with find 0 asic or lacks chips. Those are enumeration failures. This is a data-integrity failure on a chain that is talking.
• Assuming the PSU is fine because the miner boots. Enumeration happens near idle; the rail only sags at 800 W. Measure under load or you have measured nothing.
• Fitting a generic fan. The L3+ drives fan PWM at 10 kHz, not the 25 kHz used on most other Antminers — it is fixed in the control board’s PWM peripheral. A fan expecting 25 kHz can stall, and a stalled fan is a thermal CRC problem an hour later.

Related

• Nonce CRC Error in Bitcoin mining hardware — the returned-nonce half.
• Reg CRC Error troubleshooting — the register-read half.
• “Hashrate is low or a hashboard is faulty” on the L3+ — where an unfixed CRC fault ends up.
• APW3/APW3+/APW3++/APW5/APW7 PSU problems — the 12 V supplies that feed the L3+.
• ASIC Fault Finder — match your log string to a fault class.
• Start a repair — if the reflow does not hold.