How to fix “lacks chips” on Bitmain Antminer S19 ASICs

“Lacks chips” is a count mismatch, not a diagnosis. At startup the S19 control board resets the chain, broadcasts an address-assignment command down the CI line, and counts the replies coming back on RO. An S19 hash board carries 76 BM1398 chips (228 across three boards). When a chain answers with 75, or 44, or 12, the firmware raises “lacks chips” and that chain stops earning — a third of the machine. The count is the useful part: the chain breaks immediately after the last chip that answered.

What the error actually reports

• Expected: 76 chips per chain. The S19 board runs 76 BM1398s in 38 voltage domains, 2 chips per domain, about 0.36 V per domain (~13.7 V across the string). Voltage is regulated per domain, never per chip. A board expecting 114 is an S19 Pro: same BM1398, 3 chips per domain, ~0.32 V.
• The chips are daisy-chained. CLK and CI/CO run forward, RI/RO (nonces) run back, plus BI/BO and RST. A chip that dies or merely stops forwarding hides every chip behind it — the count is a position, not a quantity.
• Read it over the API: echo '{"command":"stats"}' | nc localhost 4028 → chain_acn1..3 (chips found per chain) and chain_acs1..3 (per-chip map; o = chip OK, x = chip found but erroring, - = chip never answered). On a “lacks chips” board the map ends in a run of - — the first - is chip M+1, the break.
• Turn the count into a domain. Chain 2 counts 44 → break at chip 45 → domain 23 (chips 45–46).

Likely causes, ranked

1. Cold or cracked joint on a chip’s CO, CLKO or NRSTO pin. The chip is alive; it just stops forwarding. Thermal cycling does it — the most common cause of a partial count.
2. Open passive at a domain boundary. The 33 Ω 0603 signal resistors go open, and so does the 100 nF cap coupling CLKO into the next domain’s CLKI. Suspect this first when the break lands on an odd chip number — odd chips start a new domain, so the break sits on the boundary passives. An even break number is mid-domain and points at the previous chip’s own CO/CLKO/NRSTO joint.
3. Dead chip (open). ESD, thermal abuse, silicon defect. The chain stops there.
4. Failed domain LDO. The S19 boosts ~14 V to 19 V, then LDOs step 19 V → 1.8 V → 0.8 V per domain. Shorted, the domain sits near zero; open, it is unpowered. Either way its two chips never initialise, and everything downstream goes with them.
5. 18-pin ribbon cable or connector. A bent pin or corroded contact gives counts that change between boots. Cheapest item — rule it out first.

Diagnose before you desolder anything

• Record all three counts and where the first - lands in chain_acs. A count that differs between two cold boots is a cable or an intermittent joint, not dead silicon.
• Rotate the board, not the guess. Move the suspect board to another chain position and swap its ribbon. Fault follows the board → it is the board. Fault stays with the slot → cable or control board (removing the hashboard).
• Do not reflash first. Firmware cannot recreate a solder joint; a reflash only helps when the count is correct.
• Loupe chip M+1 and its boundary passives at 10x, then thermal-image a short powered run, heatsink off: cold chip among hot neighbours = dead chip; hot passive = failed LDO or shorted cap; cold region = dead domain.

Electrical measurements

Safety, stated accurately: the domain string tops out near 13.7 V — not a shock hazard; the risk is a slipped probe shorting a domain and killing chips. The APW12 is the hazard: 200–240 V input only (it will not run on 120 V), and its PFC caps can hold ~400 V after you unplug it. Do not open it.

1. Unpowered, 30 s discharge. Black probe on a board ground pad — never the heatsink; a probe on the radiator can short the board.
2. Domain impedance sweep, 200 Ω range, across all 38 domain VDD test points. Lower than its neighbours = short; higher = open.
3. Powered domain sweep on a test fixture: stabilise 2–5 minutes, measure every domain. Within ±50 mV of each other = healthy; 100 mV+ below average = partial short; well above = open.
4. If the count is zero, not partial, check the board-wide supplies: boost output ~19 V and PIC U3 pin 2 at 3.3 V.
5. Signals at the break. S19 levels: CLK 0.7–1.3 V; CI/CO and RST 0–1.8 V; RI/RO 0.3–1.8 V, RST held high while running. CLK from crystal Y1 is a 25 MHz square wave — scope either side of the boundary passives at chip M+1.
6. Binary-search the chain. Short the RO test point to the domain rail at the chain midpoint and re-run enumeration. More chips counted → fault is downstream; same or fewer → upstream.

Board-level repair

• Passives first. Replace the open 33 Ω 0603 resistor or the 100 nF CLK coupling cap — a two-minute fix that recovers many partial-count boards. One flux-and-hot-air reflow of the suspect CO/CLKO pin is worth trying before lifting silicon.
• LDO. Check its output filter caps for a short before condemning the regulator — a shorted 22 µF output cap reads exactly like a dead LDO. S19 boards use 1.8 V and 0.8 V variants.
• Chip replacement. Hot air at 350–380 °C, flux, lift when the solder flows, wick the pads, reball with 0.4 mm balls. Verify a salvaged BM1398 in a chip test fixture before it goes on the board. BM1398 is the S19 / S19 Pro / T19 part; the BM1398AC variant is used on the S19a / S19a Pro — do not mix them. Re-apply thermal compound to every chip you uncovered. Parts: ASIC repair parts.

Verify the fix

1. Re-test from PT1 (chip scan / enumeration), then run PT3 (frequency sweep) — escalating clock and verifying hash output at each step. Skipping straight to a frequency sweep hides a joint that only fails warm.
2. The count must read 76 across a cold boot and a warm re-run, with all 38 domains inside ±50 mV.
3. Soak it hot 30–60 minutes, then re-read chain_acs. Thermal-cycling joints only reappear at temperature.

Common mistakes

• Mixing hash boards between miners. EEPROM data must match across the three boards; a board with foreign EEPROM data will not hash even with 76 healthy chips.
• Treating a domain bypass as a permanent fix. Bridging a dead domain gets a board hashing, but those chips are gone for good and the EEPROM chip count has to be edited to match.

Related

• “Chain only find 0 ASIC” — the zero-count case: boost, PIC, crystal, shorted chip.
• ANTMINER ASIC status showing ‘X’ — the chips-present-but-erroring case.
• ASIC Fault Finder — symptom → failure mode.
• Start a repair — we pull the count, isolate the domain, reball the chip.