Whatsminer M50S++

The Whatsminer M50S++ is MicroBT’s top-bin air-cooled SHA-256 miner from the 2022 M5x generation, rated at roughly 160 TH/s for about 3,520 W at the wall, or close to 22 J/TH. It was the most efficient model in the M50 line and remains a workhorse for low-cost-power operations and heat-recovery setups.

Chip and hashboard architecture

The M50S++ is built on MicroBT’s in-house SHA-256 ASIC (catalogued here as the WM3418), fabricated on a Samsung 5nm process node. That 5nm step is the defining change of the M5x platform: where the earlier M30 generation used Samsung 8nm silicon and landed around 31-38 J/TH, the move to 5nm let MicroBT roughly cut joules-per-terahash by a third while keeping the same single-box air-cooled chassis.

In keeping with the M-series air-cooled layout, the ASICs are spread across three series-wired hash boards. Unlike Bitmain’s Antminer line, a Whatsminer has no FPGA in the signal path. The control board for the M50 family is MicroBT’s CB5, built around an Allwinner H6 “CV200-OS” SoC — a quad-core 64-bit ARM Cortex-A53 with TrustZone — and the SoC talks to the ASIC chains directly over its own serial interface rather than through a Xilinx Zynq midstate engine. This is the single biggest reason Whatsminer and Antminer parts do not interchange: different SoC, different ASIC communication protocol, different hashboard EEPROM format, and different board-to-control-board connectors.

Voltage domains, not per-chip control

Like every modern SHA-256 ASIC platform, the M50S++ regulates power by voltage domain, not per individual chip. Chips are grouped into domains that share a regulated rail; within a domain the chips are wired in series for core voltage, so the domain voltage equals the per-chip voltage multiplied by the number of chips in that group. Each domain has its own regulation stage stepping the boosted board voltage down to the precise level the chip cluster needs. The practical consequence for diagnostics is important: a single shorted or open chip pulls its whole domain out of spec, and an abnormal domain voltage will take the entire hash board offline. MicroBT’s power-delivery topology and domain map differ from Bitmain’s, which is part of why repair procedures are vendor-specific.

The M50S++ also follows MicroBT’s signature integrated-PSU design: the power supply lives inside the chassis rather than as a separate brick like Antminer’s APW units. It runs on single-phase 200-240 V AC, draws through a standard C19-style inlet, and is rated for a 5-40 °C operating range with Ethernet for control.

Real-world power and efficiency

MicroBT shipped the M50S++ across an efficiency bin that spans roughly 154-162 TH/s; the higher-hashrate units sit closer to 21 J/TH while the listing here uses the nominal 160 TH/s / 3,520 W / 22 J/TH figure. As always, treat nameplate power as a floor, not the wall reading. Real consumption climbs with ambient temperature, PSU losses, and any factory or third-party tuning, and a unit pushed to the top of its frequency band will pull noticeably more than its rated wattage. Budget for the higher number when you size breakers and PDUs.

At about 75 dB and 3.5 kW in a single 200-240 V box, this is data-center-class noise and heat, not a living-room machine. The flip side is that nearly all of that 3,520 W leaves as roughly 12,010 BTU/h of usable heat — enough that ducting the exhaust into a workshop or garage turns electricity you would have spent on a heater into hashrate instead. There is real tuning headroom on the M5x platform for operators who want to trade efficiency for output or vice-versa; our ASIC power profiles resource is the place to see how frequency and voltage targets move the J/TH curve before you commit a fleet to a setting.

Specifications

Firmware compatibility

Stock, the M50S++ runs MicroBT’s proprietary btminer stack on a custom Linux build, with a web UI on port 80 and the Whatsminer JSON-RPC API on port 4028. That API is not the CGMiner protocol despite sharing the port — read commands such as summary, pools, and devs are enabled by default, while write operations (pool changes, reboot, frequency targets, OTA updates) are disabled out of the box and require token-based encryption once you enable them. Firmware is updated either over the network with MicroBT’s WhatsMinerTool utility or, for recovery, by writing an image to an SD card and booting from the control-board slot.

On third-party firmware, be honest about the landscape. The M5x platform does have aftermarket firmware options that add autotuning and custom fan curves, but the picture is different from Antminer. Braiins OS+ — the one firmware that natively speaks Stratum V2 — supports Antminer hardware only and does not run on Whatsminer, so native Stratum V2 is not on the table for an M50S++ via that route. Whatever stack you run, autotuning here is calculated at runtime from each board’s measured behavior, not a fixed table of presets, which is why two “identical” units can settle at slightly different voltages. D-Central’s own DCENT_OS effort is firmware-first and built in the same shoulders-of-giants spirit; for vendor-specific tuning today we steer M50 owners toward configurations we have validated rather than blanket flashing advice.

Common faults and troubleshooting

After three-plus years in the field, M50S++ failures cluster in a few predictable places:

• Dead or low hashboard — usually a domain fault: a shorted chip drags its rail down, an open chip breaks the serial chain so every downstream chip goes invisible, or a failed regulator starves the domain. The board reports the lost chips, but the root cause is almost always at the chip or power-management level.
• Integrated PSU faults — because the supply is inside the chassis, a PSU failure presents as a no-boot or intermittent power-cycle rather than a swap-the-brick fix.
• Thermal and fan errors — clogged fins, a failed fan, or high intake temperature trip protection and throttle or halt the unit; air-cooled M5x units are sensitive to dust and ambient.
• Network / control-board issues — a corrupted firmware or flaky SoC can be recovered by SD-card reflash before assuming hardware death.

Work the symptom methodically with our ASIC fault finder to map an error to a likely board, domain, or component before pulling anything. A proper domain-voltage audit on the bench — power off, discharge, then measure each domain test point — is what separates a five-minute chip-level fix from a needlessly scrapped board.

Repair and longevity

D-Central’s in-house technicians repair the Whatsminer M50S++. We have been doing board-level ASIC repair in Laval since 2016, and a 5nm unit at ~22 J/TH is well worth fixing rather than replacing — the efficiency gap to current-gen hardware is not large enough to write off a working chassis. Typical work includes chip-level reflow and replacement on the hash boards, voltage-domain and regulator repair, integrated-PSU service, fan and sensor replacement, and control-board recovery or substitution. Because the CB5 control board is a discrete module, board-level replacement and universal-controller paths exist for M3x/M5x hardware when an SoC is beyond recovery. Send-in repair details are on our ASIC repair page.

Who it is for and buying

The M50S++ makes sense for two buyers. First, the cost-conscious operator with cheap or behind-the-meter power: at 22 J/TH it will not win against an S21-class machine on a hosted power bill, but bought used at the right price it offers a low cost-per-terahash entry into self-hosted mining. Second, the heat-recovery user who wants real, ductable warmth from a single 240 V circuit and treats the hashrate as a bonus. It is decidedly not a quiet home unit — 75 dB belongs in a garage, shop, or dedicated mining space. New hobbyists chasing a near-silent desk miner are better served by an open-source Bitaxe-class device. To compare the M50S++ against other models on live efficiency and profitability, see our ASIC miner database and the full miner catalog.

How the M50S++ fits the lineup

Generational context

The M50S++ sits at the top of MicroBT’s 2022 air-cooled stack. It was the efficiency ceiling of the M5x family — the first WhatsMiners on Samsung 5nm — and a clear generational jump over the 8nm M30 series it replaced, dropping from roughly 31 J/TH to about 21-22 J/TH in the same form factor. It has since been superseded by the M60 series (~18-20 J/TH on a new control board with the Allwinner H616 SoC) and the 2025 M70 line (~13.5-14.5 J/TH), and on the Bitmain side it competes with the S19-XP era. That places the M50S++ firmly in the previous-generation tier: not the efficiency leader anymore, but a durable, repairable 5nm machine that earns its keep wherever power is cheap or the heat is worth recovering. Credit where due — MicroBT’s integrated-PSU, FPGA-free design is a genuinely different and elegant take on the ASIC miner, and the M50S++ is one of its better-balanced expressions.