How to fix “Chain find 0 asic” on Bitmain Antminer S17 ASICs

find 0 asic on an Antminer S17 means the control board ran its enumeration sequence on that chain and not one of the 48 hashing chips answered. Not 47, not 12 — zero. That is a different fault from a partial count: it points at the head end of the chain, the board’s power rail, or the link between the two — almost never at chip 40.

What the error actually reports

An S17 hashboard carries 48 hashing chips in 12 voltage domains of 4 chips each. Voltage is regulated per domain, not per chip: roughly 1.55 V across each domain, about 18.5 V across the chain. Three boards make the miner (144 chips), fed by an APW9 (14.5–21 V DC).

At boot, bmminer holds RST low, releases it, broadcasts CHAIN_INACTIVE, then walks SET_CHIP_ADDR down the chain over UART (115200 8N1, packets prefixed 0x55 0xAA). Commands travel forward, CI → CO, chip to chip. Responses travel backward, RO → RI, from the last chip toward the first. The firmware counts the responders and reports find 0 asic against the failing chain.

Zero responders means nothing came back from the head of the chain — either chip 1 never received the command, never answered, or its answer never made it off the board. Which of those three it is is the diagnosis. A mid-chain break gives a partial count instead — a different repair, covered in “Chain lacks chips” on the S17. The S17+ throws the same class of fault under a slightly different string: “Chain only find 0 ASIC” on the S17+.

Likely causes, ranked

1. 18-pin signal cable or connectors. The cable carries the UART command line into level shifter U1, the response line back out of U2, RST, and the chain’s clock reference. Lose one to a bent pin, corrosion or a cracked crimp and the board reads zero chips.
2. The board never got its rail. A shorted domain drags the chain voltage down and the boost stage current-limits or shuts off; a shorted MOS pass transistor or failed input cap does the same. Signature: 0 chips and a collapsed domain voltage.
3. Level shifter U1 or U2. The S17 has no per-domain shifters — only U1 and U2 at the board edge translate between the control board’s 3.3 V logic and the chain’s native levels. Kill U2 and responses never reach the controller, chain intact or not.
4. Dead clock. Cracked 25 MHz crystal or a cold joint on it. No CLK, no enumeration, 0 chips — every time.
5. Chip 1 dead, shorted or cold-soldered. A chip that is alive but fails to forward CO/CLKO/NRSTO presents identically to a dead chip. At position 1, the whole board goes invisible.
6. The control board’s UART port. Least likely; the rotation test below rules it out in a minute.

Diagnose before you desolder anything

• Rotate the cable. Swap the suspect board’s signal cable with a known-good chain’s. If find 0 asic follows the cable, you are done.
• Rotate the port. Move the board to a different chain port. Fault follows the board → the board is bad. Fault stays on the port → the control board is bad.
• Inspect at 10x. Burnt parts, missing SMD components, solder balls bridging pads, a cracked crystal, corroded pins.
• Pull the full kernel log, not the status page — our S17 kernel-log guide shows which lines fire and in what order.

Electrical measurements

Safety, stated correctly. The hashboard’s DC side tops out near 18.5 V — not a shock hazard. Treat it as a short-circuit and ESD hazard: grounded mat, and never rest the black probe on a heatsink, which shorts a domain across it. The PSU is the dangerous part: the APW9’s mains side holds roughly 400 V on its PFC capacitors after you unplug it.

1. Power input resistance, unpowered. Disconnect, wait 30 seconds for the caps to bleed, then meter across the DC input in resistance mode (a Fluke 15B+ class meter covers steps 1–4; step 5 needs a scope). Several ohms is normal; near zero is a short on the power bus (MOS, boost stage, input cap). Fix that first — powering a shorted board deepens the damage.
2. Domain impedance sweep, unpowered. Black probe on board ground (not the heatsink), red probe to each of the 12 domains. Markedly lower than its neighbours is a short in that domain; markedly higher is an open.
3. Input rail, powered on a fixture. Confirm the board receives 14.5–21 V DC. If it does not, the fault is upstream and no chain measurement means anything.
4. Domain voltage sweep, powered. Stabilise 2–5 minutes. Expect ~1.55 V per domain, all 12 within ±50 mV of one another. Any domain 100 mV or more below average is a partial short — a failed hashing chip or a blown decoupling cap in that group of 4.
5. Signal levels at the head of the chain. The documented levels for the S17e are CLK at 0.8 V ±0.1 V, with CI/CO, RI/RO and RST swinging 0–1.55 V. Use a known-good board of the same model as your reference rather than an absolute figure. Probe CI at chip 1’s input: controller talking, nothing arriving → U1 or its trace. Probe the return: RO present at chip 1, absent at the connector → U2. If the readings are ambiguous, scope the CLK test point — a stable 25 MHz oscillation, or the chain never enumerates.

Board-level repair

• Reflow before you replace. Domains clean but the chain silent? The likeliest defect is a cold joint on chip 1’s CO, CLKO or NRSTO pin, or on a domain-boundary resistor. Flux, reflow, retest before you consume a chip.
• Replacing a hashing chip. Pull the heatsink, clean the paste, flux the chip, lift with hot air at 350–380 °C, wick the pads clean. Verify the replacement on a standalone chip fixture before it goes on the board.
• Boost / MOS stage. A short on the power bus is a discrete repair, not a chip job — fix it and re-run the domain sweep before touching the chain. Parts: D-Central ASIC repair parts.

Verify the fix

A repaired board is not fixed because it enumerates. Run the full sequence:

1. PT1 — enumeration. Must read 48/48. The fixture reports failures as ASIC NG: X, X being the count of chips that did not answer.
2. PT2 — pattern test. Every chip returns correct nonces for the known test vectors. Incomplete nonce data is a partially failed chip, not a pass.
3. PT3 — frequency sweep. Heatsink assembled with fresh paste, fan running, ramp to rated frequency. “Chip reads 0 after frequency is increased” is a PT3 failure — usually a different chip than the one you replaced.

Reinstall and confirm all three chains report full chip count in the kernel log.

Common mistakes

• Reflashing firmware first. Firmware does not produce a 0-asic chain while the other two enumerate 48/48 on the same image.
• Blaming the board for a starved rail. The APW9 does run on 110/120 V at reduced output despite its label — but it will not deliver an S17’s full load there. Confirm the input rail before condemning a hashboard.

Related

• ASIC Fault Finder — log string → fault path.
• Start a repair — chip-level work on S17 boards.