Whatsminer M-Series Family Variant Decoder
Identify any MicroBT Whatsminer M-series variant at a glance: ASIC chip family, chips per board, voltage domains, control board, PSU, hashrate, power and efficiency across the M30 through M70 generations. MicroBT builds the Whatsminer line — this reference organizes their published specifications alongside D-Central’s Laval repair-bench observations into one decoder, so you can match a unit to its parts before a repair or a purchase. Voltage is regulated per domain, never per chip.
Whatsminer M-Series Family Variant Decoder
Quick answer
MicroBT builds every Whatsminer M-series miner on a pure ARM Allwinner control board with no FPGA, and its K-series SHA-256 ASIC shares the BM1397 architecture, fabbed on Samsung silicon. Voltage is regulated per stacked domain (~0.31–0.4 V), never per chip. The control board evolved Allwinner H3 (CB2) → H6 (CB4/CB5) → H616 (CB6) as the ASIC node stepped 8 nm (M3x) → 5 nm (M5x) → the M6x/M7x generations.
MicroBT publishes each Whatsminer on its own short spec card with no cross-model decoder and, unlike the per-board detail Bitmain hints at, almost no internal architecture. This is the owner's roof over the whole M-series: what generation you actually have, what silicon and control board are inside it, and where MicroBT simply does not disclose a figure (we say so rather than invent one). Specs are drawn from our own miner database and cross-checked against the Bitcoin Mining Hack Bible and our Laval repair bench.
Naming key — M3x = Samsung 8 nm (2020) · M5x = 5 nm (2022) · M6x = 2023–2024 efficiency generation · M7x = 2025–2026 latest generation. Suffixes: no suffix = base bin, S = higher-efficiency bin, S+/S++ = top bins. The 3-digit families M53 / M56 / M63 / M66 / M73 / M76 / M79 are the hydro / immersion form factors (often 380–480 V 3-phase input).
Variant decoder — every Whatsminer M-Series member, by generation
| Model | Chip (node) | Chips/board | Voltage domains | Hashrate | Power | Efficiency | Cooling | Control board (SoC) | PSU |
|---|---|---|---|---|---|---|---|---|---|
| M3x generation — Samsung 8 nm K-series (2020) — Allwinner H3 / H6 (CB2 / CB4 / CB5), 64-bit ARM, no FPGA MicroBT does not publish per-board chip counts; D-Central's K-series reverse engineering puts the M30S hash board at a chain of ~105 chips (≈315 across the three boards). Other M3x bins are shown as "not published" rather than guessed. | |||||||||
| Whatsminer M30S | K-series (KF1950) Samsung 8 nm | ~105/board (≈315/unit) * | Per-domain stacking ~0.31–0.4 V | 88 TH/s | 3344 W | 38 J/TH | Air | Allwinner H6 · CB4 | Integrated (P21-series) |
| How to identify: Chain of ~105 K-series chips per board (≈315/unit, D-Central RE figure); 22-pin control-to-hashboard ribbon; Allwinner control board with SD-card recovery slot. Notes: K-series ASIC is a BM1397 derivative (CRC-8 poly 0x31, FF-FF framing, 24 MHz ref) on Samsung 8 nm; the host bus is UART, not I2C. | |||||||||
| Whatsminer M30S+ | K-series (KF1950) Samsung 8 nm | Not published | Per-domain stacking ~0.31–0.4 V | 100 TH/s | 3400 W | 34 J/TH | Air | Allwinner H6 · CB4/CB5 | Integrated (P21-series) |
| How to identify: Higher bin of the M30S board; same 8 nm silicon. Notes: MicroBT does not publish the per-board chip count for the "+" bin. | |||||||||
| Whatsminer M30S++ | K-series (KF1950) Samsung 8 nm | Not published | Per-domain stacking ~0.31–0.4 V | 112 TH/s | 3472 W | 31 J/TH | Air | Allwinner H6OS · CB5 | Integrated (P21-series) |
| How to identify: Most-deployed M30 variant; H6OS (CV200-OS with TrustZone) on a CB5 board. Notes: The workhorse of the 8 nm generation; a common used-market and heat-reuse candidate. | |||||||||
| Whatsminer M30S++ (Hydro) | K-series (KF1950) Samsung 8 nm | Not published | Per-domain stacking ~0.31–0.4 V | 112 TH/s | 3472 W | 31 J/TH | Hydro (water) | Allwinner H6OS · CB5 | Integrated |
| How to identify: Sealed water-cooling manifold variant of the M30S++. Notes: Same silicon and board as the air M30S++; the cooling loop is the only structural difference. | |||||||||
| Whatsminer M31S | K-series (KF1950) Samsung 8 nm | Not published | Per-domain stacking ~0.31–0.4 V | 76 TH/s | 3220 W | 42.4 J/TH | Air | Allwinner H3/H6 · CB2/CB4 | Integrated (P21-series) |
| How to identify: Value tier of the 8 nm generation; wider heatsinks, lower bin. Notes: A cheap entry into an 8 nm heater; least efficient of the family. | |||||||||
| Whatsminer M32S | K-series (KF1950) Samsung 8 nm | Not published | Per-domain stacking ~0.31–0.4 V | 66 TH/s | 3432 W | 52 J/TH | Air | Allwinner H3/H6 · CB2/CB4 | Integrated (P21-series) |
| How to identify: Lowest-efficiency 8 nm bin; effectively a dedicated heater now. Notes: Best understood today as a space heater rather than a profit miner. | |||||||||
| M5x generation — 5 nm K-series (2022–2023) — Allwinner H6OS (CB5), 64-bit ARM + TrustZone, no FPGA The 5 nm K-series die was MicroBT's big efficiency step (~29 → 22 J/TH across the bins). Hydro (M53) and immersion (M56) siblings share the silicon in a rack form factor. | |||||||||
| Whatsminer M50 | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain, K-series RE) | 114 TH/s | 3306 W | 29 J/TH | Air | Allwinner H6OS · CB5 | Integrated (P21-series) |
| How to identify: First 5 nm M-series; CB5 board with TrustZone-backed secure boot. Notes: The 5 nm jump is the M5x story; the base M50 is the entry bin. | |||||||||
| Whatsminer M50S | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 126 TH/s | 3276 W | 26 J/TH | Air | Allwinner H6OS · CB5 | Integrated (P21-series) |
| How to identify: Higher bin of the M50 board. Notes: Popular efficient air miner of the 5 nm generation. | |||||||||
| Whatsminer M50S+ | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 138 TH/s | 3276 W | 23.7 J/TH | Air | Allwinner H6OS · CB5 | Integrated (P21-series) |
| How to identify: Top mid-bin of the air M50 range. Notes: Sub-24 J/TH on air made this a data-scale favourite. | |||||||||
| Whatsminer M50S++ | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 160 TH/s | 3520 W | 22 J/TH | Air | Allwinner H6OS · CB5 | Integrated (P21-series) |
| How to identify: Top air bin of the 5 nm generation. Notes: The efficiency ceiling of the M5x air line. | |||||||||
| Whatsminer M53 | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 226 TH/s | 6554 W | 29 J/TH | Hydro (water) | Allwinner H6OS · CB5 | Integrated, 380–480 V 3-phase input |
| How to identify: 19" rack chassis (~27.5 kg); sealed water manifold; 3-phase feed. Notes: Hydro sibling of the M50 silicon; needs a hydronic loop and 3-phase power. | |||||||||
| Whatsminer M53S+ | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 302 TH/s | 7248 W | 24 J/TH | Hydro (water) | Allwinner H6OS/H616 · CB5/CB6 | Integrated, 380–480 V 3-phase input |
| How to identify: Late M53 bin already carrying the newer 5 nm K-series die. Notes: Transitional part between the M5x and M6x nodes. | |||||||||
| Whatsminer M56S | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 212 TH/s | 5550 W | 26.2 J/TH | Immersion | Allwinner H6OS/H616 · CB5/CB6 | Integrated, 380–480 V 3-phase input |
| How to identify: Immersion form factor; single-phase-immersion tank fit. Notes: The M56 line is the dielectric-immersion sibling of the M5x/M6x silicon. | |||||||||
| M6x generation — 5 nm K-series (2023–2024) — Allwinner H616 (CB6, e.g. CB6V10), 64-bit quad Cortex-A53, no FPGA Bench-confirmed on an M60S: SoC = Allwinner H616 (sun50iw9p1), control board CB6V10, PSU P221B, K-series ASIC over UART. This is the most fully reverse-engineered Whatsminer generation. | |||||||||
| Whatsminer M60 | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 170 TH/s | 3383 W | 19.9 J/TH | Air | Allwinner H616 · CB6 | Integrated (P221-series) |
| How to identify: Base M6x air miner; H616 control board. Notes: MicroBT's answer to the ~20 J/TH air class; the base of the M6x line. | |||||||||
| Whatsminer M60S | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 186 TH/s | 3480 W | 18.7 J/TH | Air | Allwinner H616 · CB6V10 (bench-confirmed) | P221B (bench-confirmed) |
| How to identify: SoC ID "h616"; control board CB6V10; PSU model P221B; K-series ASIC (e.g. K32A317/K88A318 speed-binned dies) on the three K10-type hash-board slots. Notes: The reference unit for our Whatsminer reverse engineering — every field here was read off hardware. | |||||||||
| Whatsminer M60S++ | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 220 TH/s | 3960 W | 18 J/TH | Air | Allwinner H616 · CB6 | Integrated (P221-series) |
| How to identify: Top air bin of the M6x generation. Notes: Highest-hashrate air M6x; still on the H616/CB6 platform. | |||||||||
| Whatsminer M63S | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 390 TH/s | 7215 W | 18.5 J/TH | Hydro (water) | Allwinner H616 · CB6 | Integrated, 3-phase input |
| How to identify: Hydro rack sibling of the M60 silicon; ~390 TH/s per unit. Notes: A high-density hydro option for water-cooled hashcenters. | |||||||||
| Whatsminer M66S | K-series 5 nm-class | Not published | Per-domain stacking (~0.31 V/domain) | 298 TH/s | 5518 W | 18.5 J/TH | Immersion | Allwinner H616 · CB6 | Integrated, 3-phase input |
| How to identify: Immersion form factor on the newer 5 nm K-series die. Notes: The M66 line pairs a newer die with dielectric immersion. | |||||||||
| M7x generation — latest (2025–2026) — Allwinner H616 (CB6), 64-bit quad Cortex-A53, no FPGA The M7x line pushes toward ~12–14.5 J/TH. MicroBT has not published the ASIC part number for this generation, so the chip column is flagged as unconfirmed. | |||||||||
| Whatsminer M70 [UNCONFIRMED] | Next-gen K-series (part not published) | Not published | Per-domain stacking | 236 TH/s | 3422 W | 14.5 J/TH | Air | Allwinner H616 · CB6 | Integrated (P221-series) |
| How to identify: Latest-generation air miner; ~14.5 J/TH class. Notes: Chip part number is not publicly disclosed by MicroBT. | |||||||||
| Whatsminer M70S+ [UNCONFIRMED] | Next-gen K-series (part not published) | Not published | Per-domain stacking | 262 TH/s | 3275 W | 12.5 J/TH | Air | Allwinner H616 · CB6 | Integrated (P221-series) |
| How to identify: Top air bin of the M7x line (~12.5 J/TH). Notes: Among the most efficient air miners MicroBT has shipped. | |||||||||
| Whatsminer M73 [UNCONFIRMED] | Next-gen K-series (part not published) | Not published | Per-domain stacking | 512 TH/s | 7424 W | 14.5 J/TH | Hydro (water) | Allwinner H616 · CB6 | Integrated, 3-phase input |
| How to identify: High-density hydro rack unit (~512 TH/s). Notes: A hydro flagship of the current generation. | |||||||||
| Whatsminer M79 [UNCONFIRMED] | Next-gen K-series (part not published) | Not published | Per-domain stacking | 920 TH/s | 13340 W | 14.5 J/TH | Immersion | Allwinner H616 · CB6 | Integrated, 3-phase input |
| How to identify: Very high-density immersion rack unit (~0.9 PH/s per box). Notes: A hashcenter-scale immersion part; treat single-unit power (~13 kW) accordingly. | |||||||||
Voltage is regulated per voltage domain, never per chip — a group of chips shares one regulated rail (MicroBT stacks ~0.31–0.4 V domains; Canaan runs series-string groups with Vcore variable, VTOP 0.75 V, VDDIO 1.8 V). Where a cell reads "Not published", the OEM does not disclose that figure and we decline to guess; * marks a chips/board value inferred rather than OEM-stated.
Where the per-SKU numbers and fixes live
This decoder is the family map. For a single model's full spec row, its tuning bands, or a fault code, use the databases it links into — we keep the data in one place, not copied per page.
- Universal ASIC Spec Database — the full per-SKU spec row for every MicroBT model above.
- ASIC Power Profiles Database — bench-validated wall-watt vs hashrate vs J/TH tuning points.
- ASIC Fault Finder — error codes filterable by model and symptom.
- ASIC repair · flat-rate repair pricing — component-level MicroBT hash-board service on our Laval bench.
- Canaan Avalon A-Series variant decoder — the OEM sibling of this family reference (Canaan's counterpart to these MicroBT boards).
Open firmware for these boards?
DCENT_OS is D-Central's open-source (GPL-3.0) firmware, currently a closed beta targeting the Antminer S9. A Whatsminer port is research, not a shipping product: MicroBT's K-series ASIC and Allwinner secure-boot chain are still being reverse-engineered, and any port would stand on the shoulders of the open community — the ESP-Miner K-series driver work, CGMiner, and Braiins' autotuning and Stratum V2 groundwork. Stratum V2 is on the DCENT_OS roadmap, not yet shipped; among third-party firmwares only Braiins OS+ ships native SV2 today. DCENT_OS status →
Frequently asked questions
Does the Whatsminer use a PIC chip like an Antminer?
No. MicroBT builds Whatsminers on a pure ARM Allwinner SoC control board (H3, H6, then H616) with no FPGA and no Bitmain-style PIC. Voltage-enable and the ASIC bus are handled by the SoC directly over UART, so the whole "PIC fault" diagnosis from the Antminer world does not map onto a Whatsminer.
What ASIC chip does a Whatsminer use?
MicroBT's K-series SHA-256 ASIC. Reverse engineering shows it is a BM1397-architecture derivative (same CRC-8 polynomial, framing and reference clock) fabbed on Samsung silicon — 8 nm for the M3x generation (the KF1950-class die) and 5 nm from the M5x on. MicroBT does not publish a datasheet or a single marketing part number; individual dies carry speed-bin markings such as K32A317 / K88A318, read straight off our bench M60S.
How many chips per hash board does a Whatsminer have?
MicroBT does not publish per-board chip counts the way owners can derive them for Antminers. Our K-series reverse engineering puts the M30S hash board at a chain of about 105 chips (≈315 across three boards) — a derived figure, not an official MicroBT spec. For other models we deliberately show "not published" rather than guess. Voltage is regulated per stacked domain (~0.31–0.4 V), never per chip, regardless of the exact count.
Which control board is in my Whatsminer?
It tracks the generation: the M2x/M3x era used an Allwinner H3 (CB2) or H6 (CB4/CB5) board; the M30S++/M50 generation used H6OS (CB5, with TrustZone); the M60 and M70 generations use the Allwinner H616 (CB6, e.g. CB6V10). None use an FPGA. Knowing the board matters for recovery, since MicroBT flashes via a WhatsMinerTool network upload or an SD-card image.
Can you repair a Whatsminer hash board?
Yes — we diagnose and repair Whatsminer hash boards at the component level on our Laval bench, including K-series voltage-domain and signal-chain faults. Because the architecture differs from Antminer (UART bus, Allwinner control board, MicroBT EEPROM format), the playbook is Whatsminer-specific. See our ASIC repair pages for pricing and to book.
Related products, repair, and setup paths
- how D-Central diagnoses ASIC repairs
- ASIC troubleshooting library
- ASIC manuals and repair guides
- replacement hashboards
- ASIC control boards
- ASIC power supplies
- S19 family replacement hashboard
- C52 replacement control board
- APW12 S19 power supply
- immersion cooling hub
- home immersion cooling guide
- ASIC miners for immersion planning
- ASIC cooling parts
- airflow shroud before immersion
- compare miner specs in the database
- ASIC repair support
- compare ASIC miner specs
- ASIC miner database
- Antminer S9 specs
- Bitmain Antminer S9
- Antminer S9 maintenance guide
- S9 hashboard repair parts bundle
- Whatsminer M30S specs
- Whatsminer repair guide
- MicroBT Whatsminer M30S++
- Whatsminer M3x exhaust shroud
Last reviewed July 2, 2026.